Curriculum
Master the fundamentals one concept at a time.
14 topics, 2,490 interactive questions and 56 practice exams. The first 3 topics are free with no account.
- 01
Number Systems
FreeBinary, hexadecimal and octal, converting between bases, binary addition and subtraction, unsigned ranges, two's complement, sign extension and overflow.
168 steps · 100 lesson questions · about 67 min · 4 practice exams · 186 questions in total
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- Number system
- Place value
- Writing weights as powers
- Radix (base)
- The same rule in every base
- Bit
- Powers of 2 worth knowing
- MSB and LSB
- Adding a 0 on the right doubles
- Decimal → binary
- Odd or even? Look at the LSB
- Unsigned
- How much fits in n bits?
- Byte and nibble
- Hexadecimal
- The 16 nibbles
- Octal
- Binary addition
- Binary subtraction
- What about negative numbers?
- Sign bit
- Sign-magnitude's problems
- Two's complement
- Spotting the sign at a glance
- One pattern, three meanings
- Negate: invert, then add 1
- Two's complement range
- Sign extension
- Overflow
- 02
Boolean Algebra
FreeBoolean variables and operators, truth tables, the laws of Boolean algebra, De Morgan's laws and step-by-step simplification.
167 steps · 97 lesson questions · about 67 min · 4 practice exams · 179 questions in total
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- Algebra with only two values
- Boolean variable
- AND
- OR
- + is not addition
- NOT
- Bars on screen, primes when you type
- Literal
- Operator precedence
- A product picks out one input
- Truth table
- Naming the rows
- Proving and disproving
- The laws
- Identity law
- Null law
- Idempotent law
- Complement law
- Involution law
- Duality principle
- Commutative law
- Associative law
- Distributive law
- XOR and XNOR
- The strange one: OR over AND
- A letter can stand for a whole expression
- Absorption law
- Dropping a barred letter
- Combining terms
- De Morgan's laws
- De Morgan, checked
- Dual or complement?
- Sum of products (SOP)
- Product of sums (POS)
- Measuring simplicity
- A simplification strategy
- Consensus theorem
- 03
Logic Gates
FreeAND, OR, NOT, NAND, NOR, XOR and XNOR: symbols, truth tables and expressions, universal gates, and reading multi-gate circuits and waveforms.
163 steps · 98 lesson questions · about 65 min · 4 practice exams · 184 questions in total
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- What a gate does
- Three ways to describe a gate
- Reading a gate symbol
- Gate notation
- NOT gate
- Truth tables for more inputs
- AND gate
- OR gate
- Bubble
- NAND gate
- NOR gate
- De Morgan's law
- XOR gate
- An AND term picks out one row
- Where XOR is used: adding bits
- XNOR gate
- Timing diagram
- Gates on a timing diagram
- Gates with more inputs
- Odd parity (multi-input XOR)
- Reading a circuit
- Typing an expression
- One input, several gates
- Working backwards
- Universal gate
- Tying inputs together
- NOR works the same way
- Bubble pushing
- Sum of products
- 04
Combinational Logic
Full courseDesign circuits from word specifications, and use multiplexers, decoders, encoders and comparators.
141 steps · 96 lesson questions · about 56 min · 4 practice exams · 177 questions in total
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- Circuits without memory
- Combinational circuit
- Spotting memory
- The design recipe
- Turning words into logic
- Minterm
- Sum of products (Σm notation)
- The complement: the missing rows
- Always check your simplification
- Multiplexer (MUX)
- The 2:1 MUX
- Feeding signals into a MUX
- The 4:1 MUX
- Bigger MUXes from smaller ones
- A MUX can implement any function
- Decoder
- The 2-to-4 decoder
- Enable, and the DEMUX
- Demultiplexer (DEMUX)
- Building bigger decoders
- The complement trick
- Encoder and priority encoder
- Inside a plain 4-to-2 encoder
- Comparator
- Multi-bit equality
- Choosing a building block
- 05
Boolean Simplification
Full courseCanonical SOP and POS forms, minterms and maxterms, converting between them, systematic algebraic simplification, prime implicants, don't-cares and two-level NAND/NOR circuits.
134 steps · 90 lesson questions · about 54 min · 4 practice exams · 170 questions in total
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- One function, many expressions
- Conventions used here
- Minterm (recap)
- Sum of minterms (recap)
- Maxterm
- Product of maxterms (ΠM notation)
- Switching between Σ and Π
- The complement in both forms
- From any SOP to Σm
- Shortcut: patterns with dashes
- From any POS to ΠM
- Measuring cost
- Gate-input count
- Adjacent minterms
- Compare bits, not numbers
- Reusing a minterm
- Dropping redundant terms
- Simplifying a POS
- Implicant
- Prime implicant
- Don't-care condition
- Two-level logic
- SOP or POS?
- Mixed practice
- 06
Karnaugh Maps
Full courseSimplify Boolean functions visually: Gray-code layouts, grouping rules, prime implicants and don't-cares.
139 steps · 99 lesson questions · about 56 min · 4 practice exams · 180 questions in total
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- Karnaugh map
- Two variables
- Gray code ordering
- Three variables
- Four variables
- Common slip: counting cells
- Group (implicant)
- Grouping rules
- Is it adjacent?
- Reading a group
- Bigger is better
- Wrap-around adjacency
- Don't forget the edges
- An isolated 1
- Check your cover
- Prime implicant
- Essential prime implicant
- Listing prime implicants
- Don't-care condition
- Using don't-cares well
- The minimal SOP recipe
- Mixed practice
- Product of sums (POS) from a K-map
- Reading a sum term directly
- 07
Adders and ALUs
Full courseBuild binary arithmetic from gates: half and full adders, ripple-carry and carry-lookahead adders, subtraction, overflow, and a simple ALU with status flags.
140 steps · 98 lesson questions · about 56 min · 4 practice exams · 178 questions in total
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- Arithmetic from gates
- Half adder
- Reading off the gates
- Full adder
- The sum is odd parity
- The carry is the majority
- The two-level full adder
- Ripple-carry adder
- Carry numbering
- A 2-bit ripple-carry adder
- The carry has to ripple
- Gate delay model
- Counting conventions
- When does the worst case happen?
- Subtracting with an adder
- Controlled inverter
- Adder/subtractor
- Two kinds of "too big"
- Carry-out when subtracting
- Comparing by subtracting
- Beating the ripple
- Generate and propagate
- Speed and cost
- Arithmetic logic unit (ALU)
- Status flags
- 08
Latches and Flip-Flops
Full courseHow circuits remember: SR and D latches, edge-triggered D, JK and T flip-flops, and reading timing diagrams.
142 steps · 100 lesson questions · about 57 min · 4 practice exams · 185 questions in total
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- Circuits that remember
- Sequential circuit
- A quick test
- SR latch
- Leaving S = R = 1
- NAND SR latch
- Gated D latch
- Edge-triggered
- Finding edges on a waveform
- D flip-flop
- Window or camera?
- Checking your own trace
- Setup and hold time
- Characteristic table
- The D latch's equation
- JK flip-flop
- The JK characteristic equation
- T flip-flop
- Shortcut: count the toggles
- Frequency and period
- Excitation table
- Asynchronous preset and clear
- Active-low preset and clear
- Synchronous vs asynchronous reset
- Reading timing diagrams
- Identifying a device from its waveform
- 09
Registers
Full courseStoring words: parallel-load registers with load enable and clear, shift registers, shifting and rotating, register files and register transfer notation.
135 steps · 97 lesson questions · about 54 min · 4 practice exams · 177 questions in total
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- From one bit to a word
- Register
- Notation used in this topic
- The problem: loading on every edge
- Tempting but wrong: gate the clock
- Load enable
- Getting to a known value
- Asynchronous clear
- Synchronous clear
- Shift register
- Which way is right?
- SISO, SIPO, PISO, PIPO
- Moving data between registers serially
- Universal shift register
- Shift left = multiply by 2
- Logical shift right
- Arithmetic shift right
- Rounding: always downwards
- Rotate
- Shift registers that count
- Ring counter
- Johnson counter
- Register file
- The read path: one MUX per output bit
- Register transfer notation
- 10
Counters
Full courseRipple and synchronous binary counters, up/down, mod-N and BCD counters, ring and Johnson counters, and counters as frequency dividers.
130 steps · 95 lesson questions · about 52 min · 4 practice exams · 178 questions in total
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- Circuits that count
- Binary up counter
- Modulus
- The toggle rule
- Asynchronous (ripple) counter
- Which signal clocks the next stage?
- Every stage divides by 2
- Ripple delay
- Cleaning up a glitchy output
- Synchronous counter
- The next-state table
- How fast can a synchronous counter run?
- Down counter
- Up/down counter
- Count enable
- Parallel load
- Terminal count (carry out)
- Mod-N counter
- Clearing asynchronously
- BCD (decade) counter
- Ring counter
- Johnson counter
- Counters as frequency dividers
- 11
Finite State Machines
Full courseStates, state diagrams and tables, Moore vs Mealy machines, and designing sequence detectors.
130 steps · 93 lesson questions · about 52 min · 4 practice exams · 175 questions in total
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- Memory with a purpose
- State
- Finite state machine
- State diagram
- Reading a diagram
- One arrow per input
- Tracing without slipping
- Moore machine
- Mealy machine
- State table
- Which output do I write down?
- Sequence detector
- Non-overlapping version
- Where does a mismatch go? The suffix rule
- Non-overlapping in a Mealy machine
- State encoding
- Unused codes
- Equivalent states
- The design recipe
- 12
Memory
Full courseMemory as an array of words: address bits and capacity, RAM and ROM, SRAM and DRAM, ROMs as lookup tables, read/write control and building big memories from small chips.
133 steps · 95 lesson questions · about 53 min · 4 practice exams · 175 questions in total
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- From one register to thousands
- Memory, word and address
- Address bits
- Capacity and the 2ᵏ × n notation
- Convention: K, M and G
- Addresses in hex
- RAM
- ROM
- Volatile and non-volatile
- SRAM
- DRAM
- Kinds of ROM
- Inside a memory: the address decoder
- Big memories: rows and columns
- Memory control signals
- Tri-state outputs and the data bus
- A ROM is a truth table in hardware
- Wider words: chips side by side
- More words: decode the top address bits
- Byte addressing
- 13
Timing and Sequential Logic
Full coursePropagation and contamination delay, critical paths, glitches and hazards, setup and hold checks, maximum clock frequency, clock skew, synchronisers and pipelining.
134 steps · 92 lesson questions · about 54 min · 4 practice exams · 172 questions in total
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- Real gates are not instant
- Propagation delay
- Contamination delay
- Delays add along a path
- Critical path
- Speeding up a circuit
- Glitch
- Hazard
- Static-0 and dynamic hazards
- Clock
- Flip-flop timing parameters
- The register-to-register path
- Setup constraint
- Setup slack
- Many paths, one clock
- Hold constraint
- Clock skew
- Synchronous design rules
- Metastability
- Two-flip-flop synchroniser
- Pipelining
- Balancing the stages
- 14
Basic CPU / Computer Architecture
Full courseHow registers, an ALU, memory and a control FSM combine into a working CPU: instruction formats, the fetch–decode–execute cycle, tracing programs, and CPI.
134 steps · 94 lesson questions · about 54 min · 4 practice exams · 174 questions in total
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- Putting the pieces together
- Stored-program computer
- Datapath and control unit
- Meet Tiny8
- Program counter (PC)
- Instruction register (IR)
- MAR and MDR
- Accumulator and Z flag
- Instruction format
- The Tiny8 instruction set
- How many bits?
- The Tiny8 datapath
- Load enable
- Tiny8's ALU
- Buses
- Register transfer notation
- The instruction cycle
- Execute steps for every instruction
- Control signals
- Hardwired control
- Decoding with logic
- Microprogrammed control
- Tracing without slipping
- Clock period and frequency
- CPI
- CPU execution time
- Single-cycle vs multi-cycle