Glossary

Digital Logic glossary

471 terms from the course, each explained from scratch with diagrams, worked examples, common mistakes and links to practice questions. New to the subject? Start with the free first lesson.

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2-variable K-map: A 2×2 Karnaugh map for a function of A and B, with rows A = 0, 1 and columns B = 0, 1. Its cells are m0 m1 on top and m2 m3 below.
2:1 multiplexer: The smallest multiplexer: two data inputs I0 and I1, one select S and one output, with Y = I0 when S = 0 and Y = I1 when S = 1.
3-variable K-map: An 8-cell Karnaugh map for a function of A, B and C. In this course rows are A and columns are BC in Gray order: 00, 01, 11, 10.
4-variable K-map: A 16-cell Karnaugh map for a function of A, B, C and D. Rows are AB and columns are CD, both in Gray order, and the map wraps on all four edges.
4:1 multiplexer: A multiplexer with four data inputs I0–I3, two select lines S1 S0 and one output. The select code, read as a 2-bit number, picks the input.

A

Absorption law: The Boolean laws A + AB = A and A(A + B) = A: a term that contains all of another term adds nothing and can be deleted.
Access time: The delay between giving a memory a valid address (and selecting it) and the stored word appearing, valid, on its data lines.
Accumulator: A CPU register that is both an operand and the destination of every arithmetic instruction, so results build up in it.
Active-low: Describes a signal that does its job when it is 0. Active-low pins are marked with a bar, a bubble or a suffix such as _n, and appear complemented in equations.
ADD and SUB instructions: Tiny8's arithmetic instructions: ADD a does ACC ← ACC + M[a] and SUB a does ACC ← ACC − M[a], both wrapping modulo 256 and updating Z.
Adder/subtractor: A ripple-carry adder with an XOR on every B input and one control line M: M = 0 computes A + B, and M = 1 computes A + B' + 1 = A − B.
Address bits: The bits of a memory address. k address bits select one of 2ᵏ words, so N words need the smallest k with 2ᵏ ≥ N, which is log₂N rounded up.
Address decoder: The decoder that turns a memory address into one active line: inside a chip it selects one word line; in a system it selects one chip.
Address field: The bits of an instruction that give a memory address: where to find an operand, where to store a result, or where to jump.
Address range: The span of addresses from a first to a last address, inclusive. A block of N words starting at S ends at S + N − 1, and S to E holds E − S + 1 words.
Address space: The full set of addresses a processor can produce. k address lines give an address space of 2ᵏ locations, from 0 to 2ᵏ − 1.
Adjacent cells: Two K-map cells are adjacent when their input codes differ in exactly one variable. Only adjacent cells can be grouped together.
Adjacent minterms: Two minterms whose binary codes differ in exactly one bit. They combine into one product term with that variable removed.
Algebraic proof: Showing two Boolean expressions are equal by rewriting one into the other, one step at a time, with a named law justifying each step.
AND gate: A logic gate whose output is 1 only when every one of its inputs is 1. It is written AB, with the letters side by side, and acts like switches in series.
AND operation: The Boolean operation that gives 1 only when all of its inputs are 1. Written AB or A·B and called a product.
Arithmetic logic unit (ALU): A combinational circuit that performs one of several arithmetic or logic operations on its inputs, such as ADD, SUB, AND or OR, chosen by an opcode.
Arithmetic shift right: A right shift that copies the old sign bit into the MSB. For a two's complement number it divides by 2, keeping the sign and rounding down.
Assembly language: A human-readable way to write machine instructions using names like LOAD E or ADD F. An assembler turns each line into its binary word.
Associative law: The Boolean laws (A + B) + C = A + (B + C) and (AB)C = A(BC): with only one kind of operator, the grouping does not matter.
Asynchronous (ripple) counter: A counter in which only the first flip-flop sees the system clock; each later flip-flop is clocked by the stage before it, so changes ripple through.
Asynchronous clear: A clear input that forces a flip-flop or register to 0 immediately, without waiting for a clock edge, and overrides all other inputs.
Asynchronous input: A signal whose changes have no fixed timing relationship to the receiving clock, like a push button, so it can violate setup or hold.
Asynchronous preset: A flip-flop input that forces Q to 1 immediately, without waiting for a clock edge, and overrides the clock and data inputs while asserted.

B

Base conversion: Rewriting a number from one base into another without changing its value, for example from binary to decimal or from hexadecimal to binary.
Base notation: Ways of marking which base a number is written in: a subscript like 1011₂ or 2F₁₆, or a prefix in code such as 0x for hex and 0b for binary.
BCD (decade) counter: A mod-10 counter that counts 0000 to 1001 (0 to 9 in BCD) and then returns to 0000, giving one decimal digit per 4-bit stage.
Binary: The base-2 number system, which writes every value with only the digits 0 and 1. Each position is worth twice the one to its right.
Binary addition: Adding binary numbers column by column from the right, carrying 1 into the next column whenever a column's total reaches 2.
Binary counting: Counting up in base 2: 0, 1, 10, 11, 100, … Each step adds 1 at the LSB, and every 1 that overflows resets to 0 and carries left.
Binary prefixes (KiB, MiB, GiB): Unit prefixes based on powers of 2: kibi (Ki) = 2¹⁰ = 1024, mebi (Mi) = 2²⁰ and gibi (Gi) = 2³⁰. So 1 KiB is exactly 1024 bytes.
Binary state encoding: A state encoding that numbers the states 0, 1, 2, … in binary, using the fewest possible flip-flops: ⌈log₂ N⌉ for N states.
Binary subtraction: Subtracting binary numbers column by column from the right, borrowing from the left when a column needs 0 − 1. Hardware adds the two's complement instead.
Binary up counter: A counter whose n flip-flops hold a binary number that goes up by 1 at every active clock edge, wrapping from all 1s back to all 0s.
Binary-to-decimal conversion: Finding the decimal value of a binary number by adding the place weights (1, 2, 4, 8, …) of every bit that is 1.
Binary–hex conversion: Converting between binary and hexadecimal by swapping each 4-bit group (nibble) for one hex digit, grouping from the right.
Binary–octal conversion: Converting between binary and octal by swapping each 3-bit group for one octal digit (0 to 7), grouping from the right.
Bit: A binary digit: a single 0 or 1, the smallest unit of information a digital circuit stores. n bits can form 2ⁿ different patterns.
Bit slice: One bit position of a multi-bit circuit such as an ALU. An n-bit ALU is n identical slices side by side, sharing control lines and chaining carries.
Bit width: The number of bits a value or register uses. It fixes how many patterns are available, so it decides which values fit and when overflow happens.
Block carry-lookahead: A fast adder design that applies carry-lookahead within small blocks (often 4 bits) and then again between blocks, using group generate and propagate signals.
Boolean algebra: The algebra of variables that can only be 0 or 1, combined with AND, OR and NOT. It is the mathematics behind every digital circuit.
Boolean constant: One of the two fixed values in Boolean algebra, 0 (false, low) and 1 (true, high). In a circuit, a wire tied permanently low or high.
Boolean expression: A formula built from Boolean variables, the constants 0 and 1, and the operators AND, OR and NOT, such as A'B + C.
Boolean function: A rule that gives an output of 0 or 1 for every combination of 0/1 inputs. A truth table defines it completely.
Boolean notation: The symbols used to write Boolean expressions. This course uses AB for AND, A + B for OR, and a bar (typed ') for NOT.
Boolean operator: An operation that combines Boolean values to give a 0 or 1 result. The three basic ones are AND, OR and NOT.
Boolean simplification: Rewriting a Boolean expression into an equivalent one with fewer terms and literals, so the circuit needs fewer, smaller gates.
Boolean variable: A named quantity, such as A or B, that can only ever be 0 or 1. In a circuit it stands for the signal on one wire.
Borrow: In subtraction, taking 1 from the next column to the left when a column needs 0 − 1. In binary that 1 is worth 2 in the column that receives it.
Bubble: A small circle drawn on a gate's input or output meaning the signal is inverted at that point. It turns AND into NAND, OR into NOR and XOR into XNOR.
Bubble pushing: Redrawing a gate or circuit by swapping AND and OR bodies and toggling every bubble. The function stays the same; it is De Morgan's law in pictures.
Bus: A set of shared wires that carries a group of related signals, such as an address or a data word, between the parts of a digital system.
Bus contention: A fault where two or more devices drive the same bus line at the same time. If they disagree, the value is undefined and the drivers can be damaged.
Byte: A group of 8 bits, the standard unit of memory and file size. A byte holds 256 patterns: 0 to 255 unsigned, or −128 to 127 in two's complement.
Byte addressing: A memory scheme in which every byte has its own address. A 4-byte word then spans four consecutive addresses, and word i starts at byte address 4i.

C

Cache memory: A small, fast memory, usually SRAM, placed close to the processor that keeps copies of recently used data so most accesses avoid slower main memory.
Canonical form: A standard way of writing a Boolean function so that each function has exactly one such expression: the sum of minterms or the product of maxterms.
Canonical form conversion: Switching a function between its sum of minterms and product of maxterms: F = Σm(the 1-rows) = ΠM(the 0-rows), so you just take the other rows.
Carry: The 1 that moves into the next column when a column's sum is too big for one digit. In binary, a column carries when its total reaches 2.
Carry flag (C): The status flag C, which holds the adder's carry-out. After an addition C = 1 means unsigned overflow; after a subtraction here, C = 1 means no borrow.
Carry kill: A bit position where both operand bits are 0, so any incoming carry stops there: the carry-out is 0 whatever the carry-in. It cuts the ripple chain.
Carry-in: The carry that enters a column of an addition from the column to its right. A full adder has a carry-in input; a half adder doesn't.
Carry-lookahead adder: A fast adder that computes every carry directly from the generate and propagate signals and C0, instead of waiting for carries to ripple through each stage.
Carry-out: The carry produced by the most significant column of an addition, the bit that doesn't fit in the result. For unsigned addition, carry-out 1 means overflow.
Cascading counters: Chaining small counters into a larger one on a shared clock: the terminal count of each stage drives the enable of the next, like a carry.
Central processing unit (CPU): The part of a computer that fetches instructions from memory and carries them out, built from a datapath and a control unit.
Characteristic equation: A Boolean equation giving a latch's or flip-flop's next state Q⁺ in terms of its inputs and present state Q, e.g. Q⁺ = JQ' + K'Q.
Characteristic table: A table that gives a latch's or flip-flop's next state Q⁺ for every combination of its inputs and its present state Q.
Chip select (CS): A memory chip's enable input. When chip select is active the chip responds to reads and writes; when inactive it ignores them and releases the data bus.
Circuit analysis: Working out what a gate circuit does: finding its Boolean expression, evaluating it for given inputs, or building its full truth table.
Circuit cost: A measure of how expensive an expression is to build, usually counted as the number of terms, literals or gate inputs.
Clock: A square wave that repeats at a fixed rate and tells every flip-flop in a synchronous circuit when to update.
Clock cycle: One period of the clock, from one active edge to the next. A multi-cycle CPU does one register-transfer step per clock cycle.
Clock domain crossing: A signal passing from logic on one clock to logic on another, unrelated clock. To the receiver it is asynchronous and must be synchronized.
Clock enable: An input that lets a flip-flop load new data only when enabled, done with a mux in front of D while the clock stays untouched.
Clock frequency: The number of clock cycles per second, in hertz. It equals 1 ÷ clock period; 1 GHz means a billion cycles each second.
Clock period: The time for one full clock cycle, written T. It equals 1 ÷ clock frequency, so a faster clock has a shorter period.
Clock skew: The difference in arrival time of the same clock edge at two flip-flops. Here: capture time minus launch time.
Clock-to-Q delay: The longest time after a flip-flop's active clock edge until Q shows its new value. Written tcq; it is the flip-flop's propagation delay.
Combinational circuit: A digital circuit whose outputs depend only on its present inputs. It has no memory, so one truth table describes it completely.
Combinational design process: The step-by-step method for turning a word description into a circuit: name the signals, fill the truth table, write Σm, simplify, verify and draw.
Combining terms (adjacency): The rule XY + XY' = X: two terms that are identical except for one variable, plain in one and barred in the other, merge and that variable drops out.
Commutative law: The Boolean laws A + B = B + A and AB = BA: the order of the inputs to an OR or an AND makes no difference.
Comparator: A combinational circuit that compares two binary numbers and reports whether they are equal, and often which one is larger.
Comparison by subtraction: Comparing two numbers by computing A − B and reading the flags: Z for equal, the carry flag for unsigned order, and N ⊕ V for signed order.
Complement: The NOT of a value or expression: 1 becomes 0 and 0 becomes 1. Written with a bar, typed with a prime, as in A'.
Complement law: The Boolean laws A + A' = 1 and AA' = 0: a variable ORed with its complement is always 1, and ANDed with it is always 0.
Complement of a function: The function F′ that is 1 exactly where F is 0, and 0 where F is 1. In Σm/ΠM form, it uses the same indices with the other symbol.
Complementary outputs: The two outputs of a latch or flip-flop, Q and Q', which are always opposite in normal operation. Q' is free to use as an inverted copy.
Conditional branch: A jump that happens only when a condition holds, such as Tiny8's JZ, which jumps only when the zero flag is 1.
Conditional transfer: A register transfer that happens only at edges where a control signal is 1, written T1: R2 ← R1. The control signal drives the destination's load enable.
Consensus theorem: The rule XY + X'Z + YZ = XY + X'Z: when one term has X and another has X', the AND of their leftovers is redundant.
Contamination delay: The shortest time from an input change until a gate or circuit output can start to change. Written tcd; always at most tpd.
Control signals: The wires from the control unit that tell the datapath what to do each cycle: register loads, mux selects, ALU operation, memory read and write.
Control store: The small memory, usually a ROM, that holds a microprogrammed CPU's microinstructions. A micro-PC selects which one drives the signals.
Control unit: The part of a CPU that decides, in every clock cycle, what the datapath does, by driving its control signals. It is a finite state machine.
Controlled inverter: An XOR gate used as a switchable NOT: Y = B ⊕ M passes B unchanged when the control M = 0 and outputs B inverted when M = 1.
Corner group: The group made of the four corner cells of a 4-variable K-map, m0, m2, m8 and m10. Thanks to wrap-around they are mutually adjacent and read as B'D'.
Count enable: A control input that lets a counter pause: with enable = 1 it counts at each clock edge, and with enable = 0 it holds its present value.
Counter: A sequential circuit that steps through a fixed sequence of states, one step per active clock edge, usually so its outputs form a binary count.
Counterexample: One input combination where two expressions give different outputs. A single counterexample proves they are not equal.
Cover: A set of implicants that together are 1 on every 1 of the function. A minimal SOP is a cheapest cover made of prime implicants.
CPI: Cycles per instruction: the total clock cycles a program takes divided by the number of instructions it executes.
CPU execution time: How long a program takes to run: instructions executed × CPI × clock period, or equivalently instructions × CPI ÷ clock frequency.
CPU performance: How fast a CPU runs programs, measured as the inverse of execution time: instructions × CPI × clock period.
Critical path: The input-to-output path with the largest total propagation delay. Its delay is the whole circuit's tpd and limits the clock speed.
Cube notation: Writing a product term as a bit pattern with a dash for each missing variable, such as 1-0 for AC'. A pattern with k dashes covers 2ᵏ rows.
Cyclic K-map: A K-map with no essential prime implicants, because every 1 lies in two or more prime implicants arranged in a ring. It often has several minimal answers.

D

D flip-flop: An edge-triggered flip-flop that copies its D input to Q at each active clock edge and holds Q at every other time. Q⁺ = D.
Data bus: The shared group of wires that carries data words between the processor and memory or I/O. Its width equals the word size.
Data lines: The pins a memory uses to send and receive words, one per bit. A 2ᵏ × n memory has n data lines, equal to its word size.
Datapath: The part of a CPU that holds and transforms data: registers, the ALU, multiplexers and the connections to memory.
De Morgan's laws: The rules (AB)' = A' + B' and (A + B)' = A'B': to complement an AND or an OR, complement each part and swap AND with OR.
Decimal: The everyday base-10 number system, with digits 0 to 9 and place weights 1, 10, 100, 1000 and so on.
Decimal-to-binary conversion: Writing a decimal number in binary, either by subtracting the largest powers of 2 that fit or by dividing by 2 repeatedly and reading the remainders.
Decoder: A combinational circuit with n inputs and 2ⁿ outputs that sets exactly one output to 1: the one whose number matches the input code.
Decoder expansion: Building a large decoder from smaller decoders with enable inputs, so the high input bits choose which small decoder is active.
Decoder implementation: Building a function from a decoder, which supplies every minterm, plus an OR gate on the outputs for the function's 1-rows (or a NOR on its 0-rows).
Delay line: A SISO shift register used to delay a serial bit stream: an n-stage register outputs the stream n clock periods later, in the same order.
Demultiplexer (DEMUX): A combinational circuit that sends one data input to one of 2ⁿ outputs, chosen by n select lines. Every other output stays 0.
Depth expansion: Combining memory chips so each covers its own block of addresses, with a decoder on the high address bits driving the chip selects. It adds words, not bits.
Destructive read: A read that disturbs the stored value, as in a DRAM cell whose capacitor is drained by reading. The chip must write the value back after each read.
Distinguished minterm: A 1 on a K-map that is covered by exactly one prime implicant. Any prime implicant that covers a distinguished minterm is essential.
Distributive law: The Boolean laws A(B + C) = AB + AC and A + BC = (A + B)(A + C). AND distributes over OR, and OR also distributes over AND.
Don't-care condition: An input combination whose output doesn't matter, usually because it never occurs. It may be treated as 0 or 1, whichever simplifies the circuit.
Double inversion: Inverting a signal twice gives back the original. Two NOT gates in a row, or two bubbles on one wire, cancel each other out.
Down counter: A counter that subtracts 1 at each active clock edge, stepping 111, 110, … , 000 and then wrapping back to all 1s.
DRAM: Dynamic RAM: read/write memory that stores each bit as charge on a tiny capacitor. Dense and cheap, but the charge leaks, so every cell must be refreshed.
DRAM refresh: The periodic reading and rewriting of every DRAM cell, row by row, to restore the charge that leaks from its capacitors before the data is lost.
Duality principle: Swapping AND with OR and 0 with 1 throughout a true Boolean law gives another true law, called its dual.
Duty cycle: The fraction of each period that a repeating signal spends high, often given as a percentage. A 50 % duty cycle is a symmetric square wave.
Dynamic hazard: A hazard where an output that should change once can change three or more times, such as 0 → 1 → 0 → 1, before settling.

E

Edge-triggered: Describes a storage element that samples its inputs and changes state only at a clock transition (an edge), never while the clock sits at a level.
EEPROM: Electrically erasable programmable ROM: non-volatile memory that can be erased and rewritten electrically, in place, down to individual bytes.
Enable input: A control input that switches a block on or off. When an enable is inactive, a decoder holds all of its outputs at 0, whatever its other inputs say.
Encoder: A combinational circuit with 2ⁿ inputs and n outputs that outputs the binary index of its active input. The reverse of a decoder.
EPROM: Erasable programmable ROM: a ROM programmed electrically and erased by shining ultraviolet light through a window in the package, so it can be reused.
Equality comparator: A comparator that outputs 1 exactly when two binary numbers are equal, built from one XNOR per bit position followed by an AND gate.
Equivalent expressions: Two Boolean expressions are equivalent when they give the same output for every input, so they describe the same function.
Equivalent states: Two states of a state machine that no input sequence can tell apart: they give the same outputs and lead to equivalent next states for every input.
Essential prime implicant: A prime implicant that is the only one covering some 1 of the function. It must appear in every minimal sum of products, so you choose these first.
Evaluating a Boolean expression: Finding an expression's 0 or 1 value for given inputs: substitute the values, then do NOT, then AND, then OR.
Even function: A Boolean function that is 1 when an even number of its inputs are 1, counting zero as even. It is the complement of the XOR of all inputs.
Excitation table: A table listing which flip-flop input values produce each transition from present state Q to a desired next state Q⁺, using X for don't-cares.
Execute step: The part of the instruction cycle where the CPU carries out what the decoded instruction asks for, such as reading an operand or loading the PC.
Expansion to canonical form: Rewriting an SOP or POS so that every term contains every variable, by filling in each missing variable both ways. It gives the Σm or ΠM list.

F

Factoring: Pulling a literal or term shared by several products out in front of a bracket, as in AB + AC = A(B + C). It is the distributive law read backwards.
Falling edge (negative edge): The moment a signal changes from 1 to 0. Negative-edge-triggered flip-flops, drawn with a bubble on the clock pin, sample at these edges.
Fan-in: The number of inputs a logic gate has. A 3-input AND gate has a fan-in of 3; wide gates are often built from trees of 2-input gates.
Fan-out: The number of gate inputs that one signal drives. When a wire branches to several gates, every branch carries the same value.
Feedback loop: A path where a gate's output is wired back to an earlier gate's input. Feedback gives a circuit memory, so it is never found in combinational logic.
Fetch–decode–execute cycle: The loop a CPU repeats for every instruction: fetch it from memory, decode what it asks for, then execute it.
Filling a K-map: Putting a function's 1s, 0s and don't-cares into the right K-map cells, from a truth table, a minterm list or a Boolean expression.
Finite state machine: A sequential circuit with a finite set of states, a starting state, and rules that pick the next state and the outputs from the present state and inputs.
Firmware: Software stored in non-volatile memory such as ROM or flash inside a device, including the start-up program a processor runs when switched on.
Flash memory: Electrically erasable non-volatile memory that is erased in large blocks rather than byte by byte. Dense and cheap; used in SSDs, USB drives and firmware.
Flip-flop: An edge-triggered memory element that stores one bit and updates its output only at an active clock edge, holding it in between.
Flip-flop conversion: Making one type of flip-flop behave like another by driving its inputs with logic, e.g. D = T ⊕ Q turns a D flip-flop into a T flip-flop.
Flip-flop timing parameters: The four numbers that say when a flip-flop can be trusted, all measured from the clock edge: tsu, th, tcq(min) and tcq.
Forbidden state: The input combination an SR latch must never receive, S = R = 1 (or S' = R' = 0 on a NAND latch), which breaks the Q and Q' relationship.
Frequency divider: A circuit whose output repeats at a fraction of its input clock's frequency. A flip-flop that toggles every edge divides the frequency by 2.
FSM design procedure: The step-by-step method for turning a word description into a state machine circuit: states, transitions, table, encoding, equations, then a check.
Full adder: A circuit that adds three bits (A, B and a carry-in) and outputs a sum S = A ⊕ B ⊕ Cin and a carry-out Cout = AB + ACin + BCin.
Full address decoding: Generating a chip select from every address bit above the chip's own, so each address selects at most one device. Partial decoding skips bits and creates duplicate addresses.
Function select: The control bits that tell an ALU which operation to perform. With k select bits an ALU can choose among up to 2ᵏ operations.
Functional completeness: A set of gates is functionally complete if copies of those gates alone can build every possible Boolean function. {AND, OR, NOT} and {NAND} are examples.

G

Gate delay: The time one logic gate takes to respond to an input change. Counting gate delays along a path gives a simple way to compare how fast circuits are.
Gate symbol: The standard drawing used for each logic gate in a circuit diagram. The body shape gives AND, OR or XOR, and a bubble on the output adds an inversion.
Gate-input count: The total number of inputs on all the gates of a circuit, used to compare the cost of two-level implementations.
Gated clock: A clock passed through logic, such as an AND with an enable, before reaching a flip-flop. Risky: it can create glitches and clock skew.
Gated D latch: A latch with a data input D and an enable: while enabled, Q follows D (transparent); when disabled, Q holds the last value it saw.
Gated SR latch: An SR latch with an enable input: S and R only reach the latch while the enable is 1. With the enable at 0, the latch holds.
Generate and propagate signals: Per-bit signals used for fast carries: generate G = AB means the bit makes a carry by itself; propagate P = A ⊕ B means it passes an incoming carry on.
Glitch: A brief, unwanted pulse on a circuit output, caused by one input change reaching a gate along paths with different delays.
Gray code: A binary code in which consecutive values differ in exactly one bit, including the wrap from last back to first. The 2-bit sequence is 00, 01, 11, 10.
Group (K-map): A rectangle of 1, 2, 4, 8 or 16 adjacent K-map cells holding only 1s or don't-cares. Each group becomes one product term with the changing variables removed.
Grouping 0s: Finding a minimal product of sums from a K-map by grouping the 0s. Each group of 0s becomes one sum term, with each fixed variable complemented.

H

Half adder: A circuit that adds two single bits, A and B, and outputs a sum bit S = A ⊕ B and a carry bit C = AB.
HALT instruction: The instruction that stops the CPU. In Tiny8 it is opcode 0, written 00; the control unit stays in its first execute state.
Hamming distance: The number of bit positions in which two equal-length binary codes differ. K-map neighbors and consecutive Gray codes have a Hamming distance of 1.
Hardwired control: A control unit built from gates and flip-flops as a finite state machine, computing each control signal directly from the state and opcode.
Harvard architecture: A computer design with separate memories, and paths, for instructions and for data, so both can be accessed in the same cycle.
Hazard: A circuit's potential to produce a glitch for some input change, because of unequal path delays. Can be static-1, static-0 or dynamic.
Hazard-cover term: A logically redundant term, usually the consensus term, added to an expression so the output stays steady during an input change.
Hex–decimal conversion: Converting between hexadecimal and decimal: multiply each hex digit by its power of 16 and add, or divide by 16 repeatedly to go the other way.
Hex–octal conversion: Converting between hexadecimal and octal by going through binary: expand each digit into bits, then regroup the bits in threes or fours from the right.
Hexadecimal: The base-16 number system, with digits 0–9 and A–F (10–15). One hex digit stands for exactly 4 bits, so hex is a compact way to write binary.
Hexadecimal addition: Adding hex numbers column by column, where a column carries 1 into the next whenever its total reaches 16 rather than 10.
High impedance: The disconnected state of a tri-state output, written Z. The output drives neither 0 nor 1, so another device can drive the same wire.
Hold (no change): The operating condition in which a latch, flip-flop or register keeps its stored value unchanged: Q⁺ = Q.
Hold constraint: The rule that new data launched at a clock edge must not reach the next flip-flop before its hold time ends: tcq(min) + tcd ≥ th.
Hold fix: Repairing a hold violation by adding delay, usually buffers, to the short path so new data arrives after the hold window closes.
Hold slack: How much later new data arrives than a flip-flop's hold time requires: tcq(min) + tcd − th. Negative means a hold violation.
Hold time: The minimum time a flip-flop's data input must stay stable after the active clock edge so the captured value is not disturbed.

I

Idempotent law: The Boolean laws A + A = A and AA = A: repeating a variable or a term in an OR or an AND changes nothing.
Identity law: The Boolean laws A + 0 = A and A · 1 = A: ORing with 0 or ANDing with 1 leaves a value unchanged.
Implicant: A product term that is 1 only on rows where the function is 1. Whenever the implicant is 1, the function is guaranteed to be 1.
Implicate: A sum term that is 0 only on rows where the function is 0: the POS counterpart of an implicant. A prime implicate cannot lose any literal.
Implication table: A triangular chart with one cell per pair of states, used to find all equivalent states by crossing out pairs that some input sequence can tell apart.
Incompletely specified function: A Boolean function whose output is only required on some input rows; the rest are don't-cares that may be chosen freely as 0 or 1.
Initial state: The state a finite state machine is in when it starts or is reset, before any inputs have been applied. Every trace begins here.
Instruction: A single binary command a CPU can carry out, such as load, add, store or jump, stored as a word in memory.
Instruction decoding: Working out what an instruction asks for by splitting its bits into fields and identifying the opcode, by hand or with a decoder.
Instruction encoding: Turning an instruction such as STORE D into its binary word by placing each field's bits in the instruction format.
Instruction fetch: The first part of every instruction cycle: read the word the program counter points at into the instruction register and advance the PC.
Instruction format: How an instruction's bits are divided into fields, such as an opcode saying what to do and an address saying which data to use.
Instruction register (IR): The CPU register that holds the bits of the instruction currently being decoded and executed, so the control unit can read its fields.
Instruction set (ISA): The complete list of instructions a CPU understands, with their encodings and meanings. It is the contract between hardware and software.
Involution law: The Boolean law A'' = A: complementing a value twice gives back the original, so two bars over the same thing cancel.
Isolated 1: A 1 on a K-map with no adjacent 1s or don't-cares, even across the wrap. It forms a group of one cell, whose term is the full minterm.

J

JK flip-flop: An edge-triggered flip-flop with inputs J (set) and K (reset) that holds on 00, sets on 10, resets on 01 and toggles on 11.
Johnson counter: A shift register whose inverted last output feeds its serial input. Starting from all 0s, an n-bit Johnson counter cycles through 2n states.
Jump instruction: An instruction that loads the program counter with a new address, so the next instruction comes from somewhere other than the next word.

K

K-map group size: A K-map group must contain 1, 2, 4, 8 or 16 cells. A group of 2ᵏ cells in an n-variable map gives a product term with n − k literals.
K-map grouping rules: The rules for circling K-map groups: only 1s and don't-cares, power-of-two sizes, rectangles only, edges wrap, and as few, as large groups as possible.
K-map layout: How a Karnaugh map's rows and columns are labeled and where each minterm sits. This course puts A (or AB) on the rows and the rest on the columns, in Gray order.
K-map minimization: The step-by-step K-map method for finding a minimal sum of products: fill the map, take the essential prime implicants, then cover the rest with the fewest, largest groups.
Karnaugh map: A grid version of a truth table, arranged in Gray code so that neighboring cells differ in one variable. Grouping its 1s gives a minimal SOP expression.

L

Latch: A level-sensitive memory element that stores one bit and can change whenever its inputs or enable allow, not just at a clock edge.
Latch vs flip-flop: A latch is level-sensitive and follows its input while enabled; a flip-flop is edge-triggered and samples its input only at a clock edge.
Latency: The time one item takes to get all the way through a system, start to finish. In an N-stage pipeline it is N clock periods.
Laws of Boolean algebra: The equations that hold for every value of their variables, such as A + 0 = A or A + AB = A, used to rewrite and simplify expressions.
Least significant bit (LSB): The rightmost bit of a binary number, bit 0, with weight 1. It alone decides whether the number is odd (LSB 1) or even (LSB 0).
Level-sensitive: Describes a storage element that responds for the whole time its enable or clock is at the active level, as a latch does, rather than at an edge.
Literal: A single variable appearing in an expression, either plain (A) or complemented (A'). A and A' count as two different literals.
Literal count: The total number of literal appearances in an expression, counting every plain or barred letter. It measures how many gate inputs a circuit needs.
Load enable: A register control input that loads new data at the clock edge when it is 1 and makes the register hold its value when it is 0.
Load immediate (LDI): An instruction whose operand is a constant inside the instruction itself, not a memory address. LDI k puts the number k in the accumulator.
LOAD instruction: The instruction that copies a word from memory into the accumulator. In Tiny8, LOAD a does ACC ← M[a] and updates the zero flag.
Lock-up state: An unused state, or a loop of unused states, that a counter or state machine can enter at power-up and never leave, so it never reaches its proper sequence.
Logic diagram: A drawing of a digital circuit using gate symbols connected by wires, with inputs on the left and outputs on the right.
Logic gate: A small digital circuit that takes one or more binary inputs and produces one binary output by a fixed rule, such as AND, OR or NOT.
Logic level: The voltage range on a wire that a circuit reads as 0 or 1. Near 0 V is low (0); near the supply voltage is high (1).
Logical shift right: A right shift that fills the vacated MSB with 0. For an unsigned number it divides by 2, rounding down; the bit shifted out is the remainder.
Lookup table (LUT): A stored table of answers indexed by the inputs: the inputs select an entry and the stored value is the output. MUXes, ROMs and FPGA cells all work this way.

M

Magnitude comparator: A comparator with outputs G (A > B), E (A = B) and L (A < B). The most significant bit position where the numbers differ decides which is larger.
Majority function: A function that outputs 1 when more than half of its inputs are 1. For three inputs it is AB + AC + BC.
Mask ROM: A ROM whose contents are built into the chip during manufacture by the pattern of its wiring. It can never be changed afterward.
Maximum clock frequency (fmax): The fastest clock a synchronous circuit can use: 1 ÷ Tmin, where Tmin = tcq + tpd + tsu on the slowest register-to-register path.
Maximum count: The largest value a counter reaches before wrapping. An n-bit binary counter's maximum count is 2ⁿ − 1, one less than its modulus.
Maximum counting frequency: The fastest clock a counter can take and still settle correctly between edges: 1 / (n × tpd) for a ripple counter, 1 / (tpd + logic + setup) for a synchronous one.
Maxterm: A sum (OR) term containing every variable exactly once, which is 0 on exactly one row of the truth table. Mᵢ is the maxterm for row i.
Mealy machine: A finite state machine whose outputs depend on the present state and the present inputs, so they are written on the arrows as input/output.
Mealy-to-Moore conversion: Turning a Mealy machine into a Moore machine with the same behavior, by splitting each state according to the outputs on the arrows that enter it.
Memory address: The number that identifies one location in a memory. Addresses start at 0, so a memory with N words has addresses 0 to N − 1.
Memory address register (MAR): The CPU register that holds the address of the memory word being read or written. Its width equals the number of address bits.
Memory alignment: Placing each multi-byte word at an address that is a multiple of its size, so a 4-byte word starts at an address whose low two bits are 00.
Memory array: The grid of memory cells inside a memory chip, with one row per word line and one column per bit line, selected by the address decoders.
Memory bank: A group of memory chips placed side by side that share one chip select and together supply the full word width for one block of addresses.
Memory capacity: The total number of bits a memory holds: number of words × bits per word, or 2ᵏ × n for k address lines and n data lines.
Memory cell: The circuit that stores one bit in a memory array, such as a latch in SRAM, a capacitor and transistor in DRAM, or a floating-gate transistor in flash.
Memory control signals: The inputs that tell a memory chip whether and how to act: chip select (CS), read/write (R/W) or write enable (WE), and often output enable (OE).
Memory data register (MDR): The CPU register that holds the word just read from memory or the word about to be written. Its width equals the word size.
Memory density: How many bits a memory technology fits on a chip or in a given area. Smaller cells mean higher density and lower cost per bit.
Memory expansion: Building a larger memory from smaller chips: side by side for wider words (width), stacked with a decoder for more words (depth), or both.
Memory map: A table or diagram showing which device or chip occupies each range of a system's address space, with the start and end address of every block.
Memory organization (2ᵏ × n): The standard way to describe a memory's shape: number of words × bits per word, such as 1K × 8. It gives the address lines, data lines and capacity.
Memory read: The operation that copies the word stored at an address onto the data lines. The stored word is left unchanged.
Memory write: The operation that stores the word on the data lines into the location chosen by the address, replacing what was there.
Metastability: A flip-flop state stuck between 0 and 1 after D changes inside its setup-and-hold window. It resolves randomly and may take a long time.
Microinstruction: One word of a microprogram: the control-signal bits for a single clock cycle plus information about which microinstruction comes next.
Microprogrammed control: A control unit that stores each step's control signals as a microinstruction in a small ROM, stepping through them with a micro-PC.
Minimal POS: A product-of-sums expression for a function that uses the fewest possible sum terms and, among those, the fewest literals.
Minimal SOP: A sum-of-products expression for a function that uses the fewest possible product terms and, among those, the fewest literals.
Minimum clock period (Tmin): The shortest clock period that still meets setup on every path: Tmin = tcq + tpd + tsu for the slowest register-to-register path.
Minimum clock-to-Q delay: The shortest time after a flip-flop's clock edge before Q can start to change. Written tcq(min); it is the flip-flop's contamination delay.
Minterm: A product (AND) term that contains every input variable exactly once, plain or primed, so it equals 1 on exactly one row of the truth table.
Mod-N counter: A counter that steps through exactly N states, usually 0 to N − 1, and then returns to 0. N need not be a power of 2.
Mode select: Control inputs that choose which operation a multi-function register performs at the next clock edge, e.g. S1 S0 on a universal shift register.
Modulus: The number of distinct states a counter steps through before its sequence repeats. A counter with modulus N is called a mod-N counter.
Moore machine: A finite state machine whose outputs depend only on the present state, so they are written inside the state circles and change only at clock edges.
Most significant bit (MSB): The leftmost bit of a binary number, the one with the largest weight (2ⁿ⁻¹ in n bits). In two's complement it is also the sign bit.
Multi-cycle processor: A CPU that runs each instruction as several short clock cycles, one step per cycle, so it can reuse hardware and use a fast clock.
Multi-input gate: A logic gate with three or more inputs. AND, OR, NAND and NOR keep their rules; XOR becomes 1 for an odd number of 1s and XNOR for an even number.
Multiple-output circuit: A combinational circuit with more than one output computed from the same inputs. Each output gets its own column, minterm list and expression.
Multiplexer (MUX): A combinational circuit that copies one of its 2ⁿ data inputs to a single output, chosen by n select lines read as a binary number.
Multiplexer implementation: Building any Boolean function from a multiplexer: put variables on the select lines and wire each data input to 0, 1, or a leftover variable or its complement.
MUX tree: A large multiplexer built from levels of smaller ones, usually 2:1 MUXes. A 2ⁿ:1 tree of 2:1 MUXes uses 2ⁿ − 1 of them, with S0 driving the first level.

N

NAND gate: A logic gate that outputs 0 only when every input is 1, and 1 otherwise. It is an AND followed by a NOT, written (AB)', and it is a universal gate.
NAND SR latch: An SR latch built from two cross-coupled NAND gates. Its inputs are active-low: pulling S' to 0 sets Q, pulling R' to 0 resets it.
NAND-NAND logic: A two-level circuit made only of NAND gates that implements a sum of products. It is an AND-OR circuit with every gate replaced by a NAND.
Negative flag (N): The status flag N, a copy of the result's most significant bit. N = 1 means the result is negative when read as a two's complement number.
Next state: The state a sequential machine will move to at the next active clock edge, decided by its present state and its present inputs.
Next-state logic: The combinational gates in front of a state machine's flip-flops that compute the next state: one equation per flip-flop, from the present state bits and inputs.
Nibble: A group of 4 bits, half a byte. A nibble has 16 patterns, so it maps exactly to one hexadecimal digit, 0 to F.
Non-essential prime implicant: A prime implicant that is not the only cover for any 1. It may be needed to cover leftover 1s, or it may be redundant and left out.
Non-overlapping detection: A sequence detector mode in which the bits of a match are used up, so the search starts afresh after each match; 1111 then contains two matches of 11.
Non-volatile memory: Memory that keeps its contents with the power off, such as ROM, EEPROM and flash. Systems use it for start-up code and saved data.
NOR gate: A logic gate that outputs 1 only when every input is 0, and 0 otherwise. It is an OR followed by a NOT, written (A + B)', and it is a universal gate.
NOR-NOR logic: A two-level circuit made only of NOR gates that implements a product of sums. It is an OR-AND circuit with every gate replaced by a NOR.
NOT gate: A one-input logic gate, also called an inverter, whose output is always the opposite of its input: 0 becomes 1 and 1 becomes 0.
Null law: The Boolean laws A + 1 = 1 and A · 0 = 0: a 1 in an OR, or a 0 in an AND, fixes the result no matter what A is.
Number of flip-flops needed: The fewest flip-flops that can give N distinct states with binary encoding: the smallest n with 2ⁿ ≥ N, written ⌈log₂ N⌉.
Number system: A set of rules for writing quantities with a fixed set of digit symbols, such as decimal (base 10), binary (base 2) or hexadecimal (base 16).

O

Octal: The base-8 number system, with digits 0 to 7. One octal digit stands for exactly 3 bits, so binary converts to octal in groups of three.
Octal–decimal conversion: Converting between octal and decimal: multiply each octal digit by its power of 8 and add, or divide by 8 repeatedly to go the other way.
Odd function: A Boolean function that is 1 when an odd number of its inputs are 1. It is the XOR of all the inputs, such as A ⊕ B ⊕ C.
Off-by-one error: A mistake where a count or boundary is one too high or one too low, such as taking N rather than N − 1 as the last address of an N-word memory.
ON-set and OFF-set: The ON-set of a function is the set of rows where it is 1, and the OFF-set the rows where it is 0. Don't-care rows form the DC-set.
One-hot: A group of bits in which exactly one bit is 1 and all the others are 0, so the position of the 1 identifies the value.
One-hot state assignment: A state encoding with one flip-flop per state, where exactly one flip-flop is 1 at any time, trading extra flip-flops for very simple logic.
One's complement: The result of inverting every bit of a binary number. As a signed format it represents −x as the inverse of x; adding 1 turns it into the two's complement.
Opcode: The field of an instruction that says which operation to perform. A field of n bits can name up to 2ⁿ different operations.
Operand: A value an instruction works on. In Tiny8 the instruction names the operand's memory address, and the CPU reads the value from there.
Operator precedence: The rule for which Boolean operation is done first when there are no brackets: NOT first, then AND, then OR.
OR gate: A logic gate whose output is 1 when at least one input is 1, including when all of them are. It is written A + B, where the + means OR, not addition.
OR operation: The Boolean operation that gives 1 when at least one input is 1, and 0 only when all inputs are 0. Written A + B.
OR-over-AND distributive law: The Boolean law A + BC = (A + B)(A + C). It has no match in ordinary arithmetic, but it always holds in Boolean algebra.
Output enable (OE): A memory control input that lets the chip drive its data outputs during a read. With output enable inactive, the outputs stay at high impedance.
Output equation: A Boolean equation giving a state machine's output from its state bits (Moore) or from its state bits and its inputs (Mealy).
Overflow: When the true result of an arithmetic operation doesn't fit in the available bits, so the stored answer is wrong. Unsigned and signed overflow are tested differently.
Overflow flag (V): The status flag V, set when a two's complement result is wrong because it didn't fit. For an n-bit adder, V = Cₙ ⊕ Cₙ₋₁, one XOR on the top two carries.
Overlapping detection: A sequence detector mode in which the bits of one match may also count toward the next match, so 1111 contains three matches of 11.
Overlapping groups: K-map groups may share cells. Covering a 1 twice is harmless, since X + X = X, and overlapping often lets each group be larger.

P

Pairs, quads and octets: Common names for K-map groups of 2, 4 and 8 cells. A pair removes one variable, a quad removes two and an octet removes three.
Parallel load: A counter feature that copies a value from data inputs into all the flip-flops at a clock edge when LOAD = 1, instead of counting.
Parity: Whether a group of bits contains an odd or an even number of 1s. An XOR of all the bits gives 1 when the count is odd and 0 when it is even.
Parity bit: An extra bit added to data so the total number of 1s is even (even parity) or odd (odd parity), letting a receiver detect any single flipped bit.
Partial state decoding: Detecting a counter state using only some of its bits, which works when no other state the counter actually visits has those same bit values.
Path delay: The total delay along one route from a circuit input through a chain of gates to an output: the sum of each gate's delay on it.
Perfect induction: Proving a Boolean identity by checking every possible input combination in a truth table. If all rows match, the identity holds.
Pipelining: Splitting a long block of logic into stages separated by registers, so the clock can run faster and several items are in progress at once.
Positional notation: A way of writing numbers where a digit's worth depends on its position: each digit is multiplied by its place weight and the results are added.
Positional weight: The amount one unit in a given position is worth: a power of the base, bᵖ for position p counted from 0 on the right. In binary: 1, 2, 4, 8, …
Power-on reset: Forcing every flip-flop in a circuit into a known starting value when power is applied, usually through asynchronous clear and preset inputs.
Powers of 2: The numbers 1, 2, 4, 8, 16, … (2⁰, 2¹, 2², …). They are the place weights of binary and set how many patterns n bits can make.
Prime implicant: An implicant that stops being an implicant if any one of its literals is removed. It is a largest possible group of 1s.
Priority encoder: An encoder that outputs the index of the highest-priority active input when several are active, plus a valid bit V that shows whether any input is active.
Product of maxterms (ΠM): The canonical POS: an AND of one maxterm for each row where F = 0. ΠM(0, 3) means M0 · M3. It lists the 0s of the truth table.
Product of sums (POS): A Boolean expression written as an AND of OR terms, with bars only on single letters, such as (A + B')(A' + C).
Product term: An AND of one or more literals, such as AB'C. It is 1 only when every literal in it is 1.
Program counter (PC): The CPU register that holds the memory address of the next instruction to fetch. It normally adds 1 each fetch; jumps load it.
Program loop: A section of a program that repeats, built from a backward jump, with a conditional branch that exits when a count or test is met.
Program tracing: Running a program by hand, one instruction at a time, writing down every register and memory word that changes.
PROM: Programmable ROM: bought blank and programmed once by the user, typically by blowing tiny fuses. After that its contents can never be changed.
Propagation delay: The longest time from an input change until a gate or circuit output has settled at its new, correct value. Written tpd.

Q

Quine–McCluskey method: A step-by-step tabular algorithm that finds all prime implicants by combining minterms in rounds, then picks a minimal cover. It works for any number of variables.

R

Radix (base): The number of distinct digits a positional number system uses, and the factor between neighboring place weights: 10 for decimal, 2 for binary.
RAM: Random-access memory: memory that can be both read and written during normal operation, and that loses its contents when power is removed.
Random access: The ability to reach any memory location directly by its address, in about the same time regardless of which location was used before.
Range: The smallest to largest value a format can represent in n bits: 0 to 2ⁿ − 1 unsigned, and −2ⁿ⁻¹ to 2ⁿ⁻¹ − 1 in two's complement.
Read during write: What a register file's read port shows when it reads the register being written in the same cycle: the old value, until the write takes effect at the edge.
Read port: A register file's output path: a read address selects one register, and its value appears on the port's n data outputs through multiplexers.
Read/write line (R/W): The control input that tells a RAM whether an access is a read or a write. On this site R/W = 1 means read and R/W = 0 means write.
Reading a K-map group: Turning a circled K-map group into its product term: keep each variable that stays constant across the group, and drop any variable that changes.
Redundant group: A K-map group whose 1s are all already covered by other chosen groups. Dropping it leaves the function unchanged and makes the expression smaller.
Redundant literal rule: The Boolean rule A + A'B = A + B (and its dual A(A' + B) = AB): the complemented copy of a lone variable can be dropped from another term.
Redundant term: A term that can be removed from an expression without changing its output on any input, because other terms already cover every row it covers.
Register: A group of n flip-flops sharing one clock that together store an n-bit value, capturing the whole word at once on each active clock edge.
Register file: An addressed array of k registers, each n bits wide, with read ports that output a chosen register and a write port that loads one at a clock edge.
Register overhead: The part of each clock period used by the registers rather than the logic: tcq + tsu. Every pipeline stage pays it.
Register swap: Exchanging the contents of two registers. With simultaneous transfers it takes one clock edge: R1 ← R2, R2 ← R1. One transfer per edge needs a temporary.
Register transfer notation: A compact notation for what happens to registers at a clock edge, such as R1 ← R2 + R3 or T1: R2 ← R1 for a conditional transfer.
Register-to-register path: A timing path that starts at one flip-flop, passes through combinational logic, and ends at another flip-flop on the same clock.
Repeated division: A method for converting a decimal number to another base: divide by the base again and again, and read the remainders from last to first.
Result multiplexer: The multiplexer at an ALU's output that passes through the result of the operation chosen by the opcode. Every unit computes; the MUX selects one.
Ring counter: A shift register whose last output feeds its serial input, started with a single 1 so that the 1 circulates. An n-bit ring counter has n states.
Ripple delay: The total settling time of a ripple counter: each stage waits for the one below it, so in the worst case the last bit settles n × tpd after the edge.
Ripple-carry adder: An n-bit adder built from n full adders in a chain, where each stage's carry-out feeds the next stage's carry-in, so the carry ripples from LSB to MSB.
Ripple-carry delay: The time a ripple-carry adder needs before every output is correct, set by the carry crossing all n stages. It grows linearly: about 2 gate delays per bit.
Rising edge: The moment a signal changes from 0 to 1. Positive-edge-triggered flip-flops sample their inputs exactly at the clock's rising edges.
ROM: Read-only memory: non-volatile memory whose contents are set at manufacture or by programming beforehand, and only read during normal operation.
Rotate: A shift in which the bit leaving one end re-enters at the other end, so no bit is lost. After n rotations an n-bit value returns to its start.
Rounding toward negative infinity: Right shifts drop the bits that fall off, so the result is rounded down to the next lower integer: 7 shifts to 3, and −7 shifts to −4, not −3.
Row index: The decimal number of a truth-table row, found by reading its input bits as binary with A as the most significant bit. Row 6 of a 3-input table is 110.

S

Select lines: The control inputs of a multiplexer or demultiplexer. Read as a binary number, they choose which data input or output is connected.
Self-loop: An arrow in a state diagram that leaves a state and comes straight back to it: on that input, the machine stays in the same state.
Self-modifying code: A program that changes its own instructions while it runs, possible because instructions are ordinary words in the same memory as data.
Self-starting counter: A counter that, from any power-up state including unused codes, reaches its normal counting sequence within a few clock edges and then stays in it.
Sequence detector: A finite state machine that outputs 1 whenever the most recent inputs match a given bit pattern, such as 101, by tracking how much of the pattern it has seen.
Sequential circuit: A circuit whose outputs depend on its current inputs and on stored information about the past, kept in latches or flip-flops.
Serial input: The input of a shift register where a new bit enters, one bit per clock edge. It drives the D input of the first flip-flop in the chain.
Serial output: The output of the last flip-flop in a shift register. It shows the bit that will leave the register at the next shift.
Serial transfer: Moving a word from one register to another one bit per clock edge over a single wire, by connecting a serial output to a serial input.
Set and reset: To set a storage element is to make its stored bit 1; to reset (or clear) it is to make the bit 0, whatever its previous value was.
Setup constraint: The rule that the clock period must cover tcq + tpd + tsu on every register-to-register path, so data arrives in time for the next edge.
Setup slack: The spare time on a path: clock period minus (tcq + tpd + tsu). Zero or positive passes setup; negative is a setup violation.
Setup time: The minimum time a flip-flop's data input must be stable before the active clock edge for the new value to be captured reliably.
Setup violation: A timing failure where data reaches a flip-flop too late, less than tsu before the clock edge, so the wrong value may be captured.
Setup-and-hold window: The interval from tsu before to th after a clock edge during which a flip-flop's D input must not change. Its width is tsu + th.
Shannon expansion: The identity F = x'·F(x = 0) + x·F(x = 1), which splits any function on one variable. It is exactly what a 2:1 multiplexer computes.
Shift left: Moving every bit one place toward the MSB, with a 0 entering at the LSB. It multiplies the value by 2 as long as no significant bit falls off.
Shift register: A register whose flip-flops are chained so each one loads its neighbor's value, moving every bit one place along at each clock edge.
Shift right: Moving every bit one place toward the LSB: in Q3 Q2 Q1 Q0 notation, the serial input enters Q3 and the old Q0 drops out.
Short path: The input-to-output path with the smallest total contamination delay. It sets how soon any output can start to change.
Sign bit: The most significant bit of a signed number, used to show its sign: 0 for zero or positive, 1 for negative.
Sign extension: Widening a two's complement number to more bits by copying its sign bit into every new position on the left, which keeps its value the same.
Sign-magnitude: A signed number format where the MSB is a sign flag (0 = +, 1 = −) and the other bits hold the size. It has two zeros and needs special adder logic.
Signed number: A number format that can represent negative values as well as positive ones, usually by giving the most significant bit a sign role.
Signed overflow: Overflow for two's complement numbers: adding two values with the same sign gives a result with the opposite sign. Detected as carry into MSB ≠ carry out.
Signed vs unsigned: The same bit pattern means different values depending on whether it's read as unsigned (all weights positive) or signed two's complement (MSB negative).
Single-cycle processor: A CPU that completes every instruction in one long clock cycle. CPI is 1, but the period must fit the slowest instruction.
Single-literal term: A term made of just one literal, such as C' in AB + C'. It needs no first-level gate, and in NAND-NAND or NOR-NOR it enters the output gate complemented.
SISO, SIPO, PISO and PIPO: The four shift register types, named by how data gets in and out: serial or parallel input, serial or parallel output.
SR flip-flop: An edge-triggered flip-flop with set (S) and reset (R) inputs that act only at the clock edge. Q⁺ = S + R'Q, with S = R = 1 not allowed.
SR latch: A one-bit memory made of two cross-coupled NOR gates: S = 1 sets Q to 1, R = 1 resets it to 0, and S = R = 0 holds the stored value.
SRAM: Static RAM: read/write memory that stores each bit in a latch of two cross-coupled inverters. Fast and needs no refresh, but volatile and less dense than DRAM.
Stage balancing: Placing pipeline registers so every stage has about the same logic delay, since the slowest stage sets the clock for all of them.
State: A summary of everything a sequential circuit needs to remember about its past inputs, stored in flip-flops, that decides how it responds next.
State decoding: Logic that watches a counter's outputs and produces a 1 in one particular state, for example to trigger a clear, a terminal-count flag or an event.
State diagram: A drawing of a finite state machine: each circle is a state and each arrow a transition, labeled with the input that causes it and, for Mealy, the output.
State encoding: Choosing a bit pattern for each state of a finite state machine, which fixes how many flip-flops it needs and how complex its logic is.
State minimization: Removing redundant states from a state machine by finding and merging equivalent states, without changing its input/output behavior.
State table: A table form of a state machine: one row per present state, giving the next state, and the output, for every input value.
State transition: A move from one state to another, or back to the same state, at an active clock edge, drawn as a labeled arrow in a state diagram.
Static-0 hazard: A hazard where an output that should stay 0 during an input change can briefly pulse to 1, typical of product-of-sums circuits.
Static-1 hazard: A hazard where an output that should stay 1 during an input change can briefly drop to 0, typical of sum-of-products circuits.
Status flags: Single-bit ALU outputs that describe a result: N (negative), Z (zero), C (carry-out) and V (signed overflow). Programs test them to compare and branch.
STORE instruction: The instruction that copies the accumulator into a memory word. In Tiny8, STORE a does M[a] ← ACC and leaves ACC and Z unchanged.
Stored-program computer: A computer whose instructions are binary words kept in memory alongside its data, so changing the program means changing memory, not wiring.
Substitution rule: Any Boolean law stays true when each of its letters is replaced by a whole expression, used consistently throughout.
Suffix rule: For a sequence detector, the next state after any bit is the longest ending of the bits seen so far that is also a beginning of the pattern.
Sum bit: The output of an adder stage that stays in its own column: the low bit of the column's total. In a full adder, S = A ⊕ B ⊕ Cin, the odd-parity function.
Sum of minterms (Σm): A function written as the OR of one minterm per truth-table row where it equals 1, often shortened to a row list such as F = Σm(1, 2, 4).
Sum of products (SOP): A Boolean expression written as an OR of AND terms, with bars only on single letters, such as AB' + A'C + BC.
Sum term: An OR of one or more literals, such as A + B' + C. It is 0 only when every literal in it is 0.
Synchronous clear: A clear input built from logic in front of each D input, so the register resets to 0 only at the next active clock edge, not immediately.
Synchronous counter: A counter in which every flip-flop shares one clock, with gating logic deciding which bits toggle, so all bits change together at each edge.
Synchronous design: A design style where every flip-flop shares one clock and all state lives in flip-flops, so timing reduces to setup and hold checks.
Synchronous set: A set input built from logic in front of D that forces a register bit to 1 at the next clock edge, rather than immediately.

T

T flip-flop: An edge-triggered flip-flop with one input T: at each active clock edge it toggles Q if T = 1 and holds Q if T = 0. Q⁺ = T ⊕ Q.
Tautology: An expression that equals 1 for every input, such as A + A'. Its opposite, which is always 0 (like AA'), is called a contradiction.
Terminal count (carry out): An output that is 1 while a counter sits in its last state before wrapping, used to flag rollover and to chain counters together.
Throughput: How many results a system produces per unit of time. A pipeline producing one result per clock cycle has throughput equal to its clock frequency.
Tied inputs: Connecting several inputs of one gate to the same signal. A NAND or NOR with tied inputs acts as an inverter; an XOR with tied inputs is always 0.
Time and frequency units: The prefixed units used in timing work: ns (10⁻⁹ s) and ps (10⁻¹² s) for delays, MHz (10⁶ Hz) and GHz (10⁹ Hz) for clocks.
Timer: A counter used to measure time: it counts clock cycles and raises a flag or event when it reaches a set value, then usually starts over.
Timing diagram: A picture of digital signals over time: each signal is a line that is high for 1 and low for 0, with time running left to right.
Toggle: To flip a stored bit to its opposite value: 0 becomes 1 and 1 becomes 0. T = 1 on a T flip-flop and J = K = 1 on a JK flip-flop toggle Q.
Toggle rule: In a binary up counter, a bit toggles at the next edge exactly when every bit below it is 1. In a down counter, when every bit below it is 0.
Transient state: A false count that a ripple counter shows for a few nanoseconds while a change is still rippling through its stages, before it settles.
Tri-state buffer: A buffer with an enable input. When enabled it passes its input through; when disabled its output is disconnected (high impedance, Z), driving neither 0 nor 1.
Truth table: A table that lists every possible combination of input values and the output for each one. With n inputs it has 2ⁿ rows.
Two-dimensional decoding: Arranging memory cells in a grid and decoding the address in two halves, one for the row and one for the column, so the decoders stay small.
Two-flip-flop synchronizer: Two flip-flops in series on the receiving clock that an asynchronous input passes through, giving any metastability a full cycle to settle.
Two-half-adder full adder: A full adder made from two half adders and an OR gate: the first adds A and B, the second adds the carry-in, and the OR merges their carries.
Two-level full adder: A full adder built directly from its minimal equations in two levels of logic: a 3-input XOR for S, and three ANDs feeding a 3-input OR for Cout.
Two-level logic: A circuit in which every input passes through at most two levels of gates, such as AND-OR for an SOP or OR-AND for a POS.
Two's complement: The standard way to store signed integers: ordinary binary except the MSB has weight −2ⁿ⁻¹. n bits cover −2ⁿ⁻¹ to 2ⁿ⁻¹ − 1.
Two's complement negation: Changing the sign of a two's complement number by inverting every bit and then adding 1. It works in both directions, from + to − and back.
Two's complement subtraction: Subtracting by adding the negative: A − B is computed as A + (B inverted) + 1, so the same adder circuit handles both addition and subtraction.

U

Universal gate: A gate type that can build NOT, AND and OR on its own, and so any Boolean function. NAND and NOR are the two universal gates.
Universal shift register: A register that can hold, shift right, shift left or load in parallel, with the operation picked by two mode-select inputs S1 S0.
Unsigned number: A binary number with no sign: every bit has a positive weight, so n bits represent the whole numbers 0 to 2ⁿ − 1.
Unsigned overflow: Overflow for unsigned numbers: an addition's true sum needs more bits than are available, shown by a carry-out of 1 from the most significant bit.
Unused BCD codes: In 4-bit BCD only 0000 to 1001 (digits 0 to 9) occur, so codes 1010 to 1111 (minterms 10 to 15) are don't-cares when simplifying BCD circuits.
Unused states: Bit patterns that a counter's or state machine's flip-flops can hold but never visit in normal operation, such as 1010 to 1111 in a BCD counter.
Up/down counter: A counter with a direction input, often called U: when U = 1 it counts up at each clock edge, and when U = 0 it counts down.

V

Valid bit: An extra priority-encoder output that is 1 when at least one input is active, so an all-zero code can be told apart from no input at all.
Volatile memory: Memory that loses its contents when the power is removed. SRAM and DRAM, and so ordinary RAM, are volatile.

W

Width expansion: Placing memory chips side by side, sharing address and control lines, so together they form a wider word. The number of words stays the same.
Word (memory): The fixed-size group of bits stored at one memory address and always read or written as a unit. Its width is the memory's word size.
Word address: The number of a whole word in memory. In a byte-addressable memory with 4-byte words, word n starts at byte address 4n, and the word number is the byte address ÷ 4.
Word line: A wire driven by a memory's address decoder that runs along one row of cells. When it is 1, that row is connected to the data (bit) lines.
Word size: The number of bits in each word of a memory: the n in 2ᵏ × n. It sets the number of data lines, independently of how many words there are.
Wrap-around adjacency: On a K-map, cells at opposite ends of a row or column are adjacent, as if the map were rolled into a tube or torus. Groups may wrap across edges.
Wraparound: The way fixed-width arithmetic rolls over: a result too big or too small for n bits keeps only its low n bits, so values repeat every 2ⁿ, like a clock.
Wraparound (counter): What a counter does after its last state: an up counter goes from its maximum back to 0, and a down counter goes from 0 back to its maximum.
Write enable (WE): A control signal that permits a write: in a register file, the addressed register loads new data at the clock edge only when the write enable is on.
Write port: A register file's input path: write data, a write address and a write enable. At a clock edge with the enable on, the addressed register loads the data.

X

XNOR gate: A logic gate whose output is 1 when its two inputs are equal and 0 when they differ. It is an XOR with an inverted output, also called the equivalence gate.
XOR gate: A logic gate whose output is 1 when its two inputs are different and 0 when they match. Written A ⊕ B, it equals A'B + AB'.
XOR identities: The rules for simplifying XOR: A ⊕ 0 = A, A ⊕ 1 = A', A ⊕ A = 0 and A ⊕ A' = 1, plus the commutative and associative laws and self-cancelling.

Z

Zero detector: A circuit that outputs 1 only when every bit of a word is 0. For n bits it's a single n-input NOR gate (or an OR followed by NOT). It produces the Z flag.
Zero flag (Z): A 1-bit status register that is 1 when the last result loaded into the accumulator was zero. Conditional jumps test it.