A processor sees one long address space. A memory map shows who owns each part of it: which addresses belong to RAM, which to ROM, which to I/O devices, and which are empty.
Each entry is an address range: a first address, a last address, and the device. For example, in a 16-bit space:
- 0000₁₆–7FFF₁₆: 32K RAM
- 8000₁₆–8FFF₁₆: 4K I/O
- 9000₁₆–DFFF₁₆: unused
- E000₁₆–FFFF₁₆: 8K ROM
The map is more than documentation. Each block's chip select comes straight from it: the address bits above the chip's own bits are fixed across its block, and ANDing them gives the select. Blocks start at multiples of their size, which keeps those fixed bits clean.
When every high bit is checked, each address belongs to at most one device (full address decoding). Checking fewer bits makes a device appear at several places in the map.
Microcontroller datasheets begin with exactly this kind of table, placing flash, SRAM and each peripheral at fixed addresses.
| 0 | 0 | 0 | 0 | 1 | 0 | 0 |
| 0 | 0 | 0 | 1 | 1 | 0 | 0 |
| 0 | 0 | 1 | 0 | 1 | 0 | 0 |
| 0 | 0 | 1 | 1 | 1 | 0 | 0 |
| 0 | 1 | 0 | 0 | 1 | 0 | 0 |
| 0 | 1 | 0 | 1 | 1 | 0 | 0 |
| 0 | 1 | 1 | 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 | 1 | 0 | 0 |
| 1 | 0 | 0 | 0 | 0 | 1 | 0 |
| 1 | 0 | 0 | 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 | 0 | 0 | 0 |
| 1 | 0 | 1 | 1 | 0 | 0 | 0 |
| 1 | 1 | 0 | 0 | 0 | 0 | 0 |
| 1 | 1 | 0 | 1 | 0 | 0 | 0 |
| 1 | 1 | 1 | 0 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 0 | 0 | 1 |