Data bus

Also called: data bus lines, shared data bus, data path bus

The shared group of wires that carries data words between the processor and memory or I/O. Its width equals the word size.

The data bus carries the words themselves: from memory to the processor on a read, and from the processor to memory on a write. It is a two-way bus.

Its width is the number of data lines, which equals the word size. A ×8 memory system has an 8-bit data bus, D7–D0.

Every memory chip in the system connects to the data bus (or, when chips sit side by side, to its own slice of it). Only one may drive it at a time:

During a read, only the selected chip drives; the rest have their tri-state outputs at high impedance.
During a write, the processor drives and the selected chip listens.

That's why memory outputs are tri-state. Without them, every chip would drive the bus all the time and bus contention would be unavoidable.

Compare the address bus, which only ever carries addresses from the processor outward. Its width counts the words (address bits); the data bus width is the size of each word. The two are independent.

Worked example

Example

Splitting a wide data bus

A 1K × 16 memory is made of four 1K × 4 chips. How do they attach to the 16-bit data bus?

1.
Chip 0 connects to D3–D0, chip 1 to D7–D4, chip 2 to D11–D8, chip 3 to D15–D12.
2.
All four are selected together, so on a read all four drive their own slices at once.
3.
No two chips share a data line, so there's no contention.

Common mistakes

Sizing the data bus by the number of words. Its width is the word size.
Letting two chips drive the same data lines at once. Only the selected chip may drive.
Thinking data flows only from memory. On a write, the processor drives the data bus.