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D flip-flop

Also called: DFF, D flip flop, D-type flip-flop, data flip-flop, delay flip-flop, D-FF, positive-edge-triggered D flip-flop

An edge-triggered flip-flop that copies its D input to Q at each active clock edge and holds Q at every other time. Q⁺ = D.

The D flip-flop is the most widely used storage element in digital design. Its rule fits in one line: at each rising clock edge, Q copies D. At all other times, Q holds.

Its characteristic equation is simply Q⁺ = D. The old Q has no say in what is loaded.

Think of a camera. At each rising edge it takes one photo of D, and Q shows that photo until the next edge. Whatever D does between photos is never seen.

Why it is everywhere:

  • Put n of them on one clock and you have a register.
  • Chain them and you have a shift register.
  • Put logic in front of D and it can imitate any other flip-flop: drive D with the next-state expression you want. This is flip flop conversion.
  • Because it is edge triggered, data moves exactly one stage per clock, never further.

The "D" stands for data (or delay): Q looks like D, delayed until the next edge.

To work reliably, D must be steady for the setup time before the edge and the hold time after it. Many D flip-flops also have preset and clear pins.

CLKDQ

Worked examples

Example

Tracing the diagram above

Positive-edge D flip-flop, Q starts at 0. Mark the rising edges first: slots 3, 7 and 11.

  1. 1.

    Slots 1–2: before the first edge, Q = 0.

  2. 2.

    Slot 3: edge, D = 1. Q becomes 1.

  3. 3.

    Slots 4–6: no edge. D pulses to 1 in slot 5 and back, but Q ignores it and stays 1.

  4. 4.

    Slot 7: edge, D = 0. Q becomes 0.

  5. 5.

    Slot 11: edge, D = 1. Q becomes 1. D falls in slot 12, too late to matter.

Example

A D flip-flop that toggles

Wire back to D. Q starts at 0. What happens over four rising edges?

  1. 1.

    Before edge 1: Q = 0, so D = = 1.

  2. 2.

    Edge 1: Q loads 1. Now D = 0.

  3. 3.

    Edge 2: Q loads 0. Edge 3: Q = 1. Edge 4: Q = 0.

  4. 4.

    Q flips at every edge, exactly like a T flip-flop with T = 1. It is a divide-by-2 frequency divider.

Common mistakes

  • Letting Q follow D while the clock is high. That is a D latch, not a flip-flop.

  • Reading D just after the edge. Use the value D has at the edge, which equals its value just before.

  • Forgetting the starting value of Q before the first edge.

Practice D flip-flop

Interactive questions with instant feedback and a worked solution for every wrong answer.

Learn it step by step

D flip-flop is taught in Latches and Flip-Flops, Registers, Counters and Timing and Sequential Logic.