Overflow flag (V)

Also called: V flag, overflow detector, signed overflow flag

The status flag V, set when a two's complement result is wrong because it didn't fit. For an n-bit adder, V = Cₙ ⊕ Cₙ₋₁, one XOR on the top two carries.

The overflow flag V records signed overflow: the twos complement result is outside the signed range, so its bits read as the wrong number.

The hardware is one XOR gate on the top two carries of the adder:

V = Cₙ ⊕ Cₙ₋₁

Cₙ is the carry out of the sign bit and Cₙ₋₁ is the carry into it. In a 4-bit adder V = C4 ⊕ C3; in an 8-bit adder, V = C8 ⊕ C7.

An equivalent form uses only sign bits: overflow happens when both operands have the same sign and the result has the other. For 4 bits, V = . For a subtraction, use the sign of B as the adder sees it, after the XOR.

V is for signed numbers only. For unsigned arithmetic, check the carry flag instead. The two flags are independent, and all four combinations of C and V occur.

Common wiring mistakes in lab ALUs: using the carry-out as V, keeping C4 ⊕ C3 after widening a design to 8 bits (that checks the middle of the number, not the sign bit), and judging a subtraction by the sign of the original B.

Worked examples

Example

−6 + (−4) in 4 bits

1010 + 1100. The true sum, −10, is below −8.

1.
Bit 0: 0 + 0 = 0. Bit 1: 1 + 0 = 1. Bit 2: 0 + 1 = 1, no carry, so C3 = 0.
2.
Bit 3: 1 + 1 = 10₂. Write 0, carry 1, so C4 = 1.
3.
V = C4 ⊕ C3 = 1 ⊕ 0 = 1. The result 0110 reads +6: two negatives gave a positive.

Example

4 + (−3) in 4 bits

0100 + 1101. Bit 2 is 1 + 1, so C3 = 1, and bit 3 is 0 + 1 + 1, so C4 = 1. V = 1 ⊕ 1 = 0. The result 0001 = 1 is correct, even though there's a carry-out.

Common mistakes

Using the carry-out as V.
Keeping C4 ⊕ C3 in a wider ALU. Use the two carries around the actual sign bit.
Applying the sign rule to the original B in a subtraction.

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Overflow flag (V) is taught in Adders and ALUs and Basic CPU / Computer Architecture.

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