Signed overflow happens when the true result of a twos complement operation is outside the signed range, so the stored bits read as the wrong number, with the wrong sign.
The sign rule for addition:
- two positives giving a negative: overflow
- two negatives giving a positive (or zero): overflow
- a positive plus a negative: never overflows, because the result lies between the two operands
The hardware rule: compare the carry into the MSB column with the carry out of it. If they differ, it's signed overflow. In an n-bit adder that's V = Cₙ ⊕ Cₙ₋₁, a single XOR gate. The two rules always agree.
Why? With two positive inputs, the sign column adds 0 + 0 + carry-in, so the result's MSB equals the carry-in, and a carry-in of 1 makes the result look negative. With two negatives, the column adds 1 + 1 + carry-in, which always carries out, and a carry-in of 0 leaves the result looking positive. With mixed signs, the carry-in and carry-out are always equal.
For subtraction A − B, apply the sign rule to the numbers the adder actually adds, A and −B. Processors record the result in the overflow flag V.