A delay line delays a stream of bits by a fixed number of clock periods. The digital version is simply a SISO shift register (serial in, serial out; see siso sipo piso pipo).
How it works: each flip-flop holds a bit for exactly one clock period before passing it on. With n stages, every bit spends n periods inside, so the output stream is the input stream delayed by n clock periods. Nothing is lost or reordered: first in, first out.
Sizing rule: a delay of N clock periods needs N flip-flops. A single d flip flop is a delay line of one period.
Counting edges: a bit that enters at edge k is in stage 1 after edge k, stage 2 after edge k + 1, and reaches the last stage of an n-stage line at edge k + n − 1.
Where they are used: lining up two signals that took paths of different lengths through a circuit, building digital filters (each tap is an earlier sample), and detecting patterns in a stream by looking at the last n bits at once.