Fetch–decode–execute cycle

Also called: fetch-decode-execute cycle, instruction cycle, fetch-execute cycle, fetch-decode-execute, machine cycle

The loop a CPU repeats for every instruction: fetch it from memory, decode what it asks for, then execute it.

A CPU does the same three things over and over, for as long as it runs:

Fetch: read the instruction the program counter points at, and advance the PC.
Decode: work out what the instruction asks for, from its opcode.
Execute: carry it out.

Then it starts again with the next instruction.

In Tiny8, each step of the cycle is one or more clock cycles:

F1 MAR ← PC
F2 MDR ← M[MAR], PC ← PC + 1
F3 IR ← MDR
D decode IR[7:4]; MAR ← IR[3:0]
E1 and possibly E2, depending on the instruction.

Fetch and decode are identical for every instruction; only execute differs. So LOAD, STORE, ADD and SUB take 3 + 1 + 2 = 6 cycles, and JMP, JZ and HALT take 3 + 1 + 1 = 5.

HALT is the only way out: it leaves the control unit stuck in E1, so the loop stops.

Worked example

Example

One full cycle for JMP

Tiny8's PC = 6, and M[6] = 52 (JMP 2).

1.
F1: MAR = 6.
2.
F2: MDR = 52, PC = 7.
3.
F3: IR = 52.
4.
D: opcode 5 = JMP. MAR = 2 (unused by JMP, but harmless).
5.
E1: PC = 2. The next fetch starts at address 2. Five cycles in all.

Common mistakes

Incrementing the PC during execute. Tiny8 does it in F2, so the PC already points past the instruction when it runs.
Thinking decode changes depending on the instruction. Fetch and decode are the same every time.

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Fetch–decode–execute cycle is taught in Basic CPU / Computer Architecture.

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