Control unit

Also called: CU, CPU control unit

The part of a CPU that decides, in every clock cycle, what the datapath does, by driving its control signals. It is a finite state machine.

The control unit is the CPU's director. It doesn't store or compute data itself. In every clock cycle it sets the control signals: which registers load, what each multiplexer selects, what the ALU does, and whether memory reads or writes. The datapath then does exactly that at the clock edge.

Under the hood it's a finite state machine:

its state is the current step, such as F1, F2, F3 (fetch), D (decode), E1, E2 (execute);
its inputs are the decoded opcode from the IR and status bits like the zero flag;
its outputs are the control signals.

There are two classic ways to build one:

Hardwired: gates compute each signal from the state and opcode. Fast, but every change is a redesign.
Microprogrammed: the signals for each step are stored as words in a small ROM, the control store. Slower per step, but easy to change.

Either way, the control unit's job is to answer two questions per cycle: which register changes, and where its new value comes from.

Worked example

Example

Steps for a STORE and a JZ

Using the Tiny8 control FSM above ('mem' = LOAD, STORE, ADD, SUB; 'jump' = JMP, JZ), list the states for STORE C, then for JZ 4.

1.
STORE C: F1, F2, F3, D, E1, then 'mem' sends it to E2, then back to F1. Six cycles.
2.
In E1 the control unit sets MDRsrc = 1 and LdMDR = 1 (MDR ← ACC). In E2 it sets Write = 1.
3.
JZ 4: F1, F2, F3, D, E1, then 'jump' sends it straight back to F1. Five cycles, whether the jump is taken or not.
4.
In E1 of the JZ, it sets PCsrc = 1 and drives LdPC with Z, so the PC loads 4 only when Z = 1.

Common mistakes

Thinking the control unit does the arithmetic. The ALU, in the datapath, does that.
Making fetch steps depend on the opcode. During F1 and F2 the IR still holds the previous instruction.

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Control unit is taught in Basic CPU / Computer Architecture.

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