4:1 multiplexer

Also called: 4:1 MUX, 4-to-1 multiplexer, 4-to-1 MUX, four-input multiplexer, 4x1 MUX

A multiplexer with four data inputs I0–I3, two select lines S1 S0 and one output. The select code, read as a 2-bit number, picks the input.

A 4:1 multiplexer passes one of four data inputs to its output. Two select lines, S1 and S0, form a 2-bit code. S1 is the MSB, so the code is 2·S1 + S0:

S1 S0 = 00 → Y = I0
S1 S0 = 01 → Y = I1
S1 S0 = 10 → Y = I2
S1 S0 = 11 → Y = I3

Each data input is ANDed with the minterm of its own code, and the four products are ORed:

Y =

For any select code, three of the four AND gates contain a 0 literal, so only one data input reaches the output.

The 4:1 MUX is the workhorse of multiplexer implementation: put two of a function's three variables on the selects, and the third (or a constant) on each data input, and one 4:1 MUX builds any 3-variable function. You can also assemble one from three 2:1 MUXes as a small mux tree.

Worked examples

Example

Reading the output

I0 = 1, I1 = 0, I2 = 0, I3 = 1, and S1 S0 = 11.

1.
11₂ = 3, so Y = I3 = 1.
2.
Check with the equation: = 1 · 1 · 1 = 1, and every other term contains or , which are 0.
3.
Change to S1 S0 = 10: Y = I2 = 0.

Example

Selecting a particular input

You want the output to show I2. What must the selects be?

1.
2 in binary is 10.
2.
S1 is the MSB, so S1 = 1 and S0 = 0.
3.
Swapping them (S1 = 0, S0 = 1) would select I1 instead.

Common mistakes

Reading S0 as the MSB. With S1 S0 = 01, the selected input is I1, not I2.
Thinking a 4:1 MUX has four select lines. Four inputs need only two selects (2² = 4).
Forgetting that only one data input can reach Y. The output is never an OR of several inputs.

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4:1 multiplexer is taught in Combinational Logic.

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