The instruction register holds the instruction the CPU is working on: all of its bits. The control unit reads the opcode field to decide what to do, and the datapath uses the other fields (in Tiny8, the 4-bit address) as an operand address or jump target.
In Tiny8 the IR is 8 bits:
- IR[7:4] is the opcode, which feeds a 4-to-16 decoder;
- IR[3:0] is the address field, which can be copied into the MAR or the PC.
How it gets loaded: during fetch, the instruction word comes from memory into the MDR, then step F3 copies it: IR ← MDR. That frees the MDR for operand data in the execute steps, while the IR keeps the instruction steady.
Two facts to keep straight:
- The IR holds the instruction's bits, not its address. The address it came from was in the PC.
- Until F3's edge, the IR still holds the previous instruction. That's why the fetch steps can't depend on the opcode.
0
128
1
64
0
32
0
16
1
8
0
4
0
2
1
1