Output enable controls the tri-state buffers on a memory chip's data outputs. Even when the chip is selected and set to read, it only puts the word on the data lines while OE is active.
- CS active, read, OE active → the stored word appears on the data lines.
- CS active, read, OE inactive → the outputs stay at high impedance (Z).
- CS inactive → outputs at Z, whatever OE is.
Why have a separate pin when chip select already exists? It gives the system finer timing control. The chip can be selected early, so its internal read (the access time) starts, while OE waits until the data bus is free. That avoids bus contention with whichever device used the bus just before.
On real chips OE is usually active low, so the chip drives the bus when the OE pin is 0. Together with CS and a write enable, it forms the usual trio of memory control signals.