Access time

Also called: memory access time, read access time, memory latency

The delay between giving a memory a valid address (and selecting it) and the stored word appearing, valid, on its data lines.

When you start a memory read, the word doesn't appear instantly. The address has to pass through the address decoder, the selected row has to drive its bit lines, and the output buffers have to switch. The total delay is the access time.

Until it has passed, the data lines may hold anything. So whatever copies the word, usually a processor register, must wait at least the access time after the address and chip select are valid.

Typical scales:

on-chip SRAM caches: around a nanosecond
DRAM main memory: tens of nanoseconds
flash: microseconds for a read

When memory is slower than the processor's clock, the processor waits extra clock cycles for each access. That gap is why systems put a small fast cache between the processor and main memory.

Worked example

Example

Wait cycles

A processor runs at 100 MHz. Its memory has an access time of 25 ns. How many clock cycles must a read take?

1.
Clock period: 1 ÷ 100 MHz = 10 ns.
2.
25 ns ÷ 10 ns = 2.5 cycles.
3.
A read can only finish on a clock edge, so round up: 3 cycles.

Common mistakes

Reading the data as soon as the address is applied. The word is valid only after the access time.
Rounding wait cycles down. Finishing early means sampling data that isn't valid yet.

Practice Access time

Interactive questions with instant feedback and a worked solution for every wrong answer.

Memory lesson full course

Put the steps of a read from memory in order.

Learn it step by step

Access time is taught in Memory and Timing and Sequential Logic.

Memory →Timing and Sequential Logic →

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