Read during write describes a register file cycle in which a read port reads the same register that the write port is writing.
The rule follows from how the parts work:
- Reading is combinational: the read MUX shows whatever the register's flip-flops hold right now.
- Writing changes the flip-flops only at the rising edge.
So during the cycle, before the edge, the read port shows the old value. After the edge, it shows the new one.
Why it matters in a CPU: suppose one instruction writes R1 and the very next one reads R1. If the read happens in the same cycle as the write, the second instruction would get a stale value. Pipelined processors handle this with tricks such as writing in the first half of the cycle and reading in the second, or a bypass (forwarding) path that sends the new value straight to the reader.
In this course, assume the simple behavior: a read sees the value stored before the edge.