A write port puts a value into one register of a register file. It has three parts:
- the write data, n bits, sent to every register,
- the write address, log₂ k bits, which picks one register,
- the write enable W, which says whether to write at all.
How it is built: every register is a load enable register. A decoder turns the write address into one-hot lines, and each line is ANDed with W to make that register's load enable. For 4 registers, register 2's load enable is L2 = .
The sequence of events for one write:
- The address, data and W = 1 are set up during the cycle.
- The decoder and AND gates raise exactly one load enable.
- At the rising edge, that register loads the data; all others hold.
Writing happens only at the edge, unlike reading, which is combinational. With W = 0 every load enable is 0, so nothing changes even if the address and data lines are busy.
The output path is the read port.