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Register file

Also called: regfile, register bank, register array, general-purpose registers, GPR file

An addressed array of k registers, each n bits wide, with read ports that output a chosen register and a write port that loads one at a clock edge.

A register file is a small, fast memory made of registers. It holds a CPU's general-purpose registers, such as R0–R7.

Its parts:

  • Storage: k load enable registers, each n bits wide, for k × n bits in total.
  • Address: log₂ k bits pick one register. 8 registers need 3 address bits; 32 need 5.
  • Write port: a write address, n data bits and a write enable W. At a rising edge with W = 1, only the addressed register loads the data.
  • Read port: a read address selects a register, whose value appears on n output bits. Most register files have two read ports and one write port, so an instruction like ADD R1, R2, R3 can read two operands and write one result each cycle.

How it is built:

  • Write: a decoder turns the write address into one-hot lines, each ANDed with W to form that register's load enable.
  • Read: for each output bit, a k:1 multiplexer picks that bit from the addressed register. A second read port needs a second, independent set of MUXes.

Reading is combinational and writing happens at the edge. So a read of the register being written shows the old value until the edge; see read during write.

Compared with main memory (ram), a register file is tiny but can be read and written in the same cycle with very little delay, which is why the CPU's working values live there.

WAL0L1

Worked examples

Example

Sizing a register file

A register file has 64 registers of 16 bits, two read ports and one write port. Work out its size and read logic.

  1. 1.

    Storage: 64 × 16 = 1024 bits, so 1024 flip-flops.

  2. 2.

    Address bits: log₂ 64 = 6 per port.

  3. 3.

    Each read port needs 16 MUXes of size 64:1, one per output bit. Two read ports need 32.

  4. 4.

    Each 64:1 MUX has 6 select lines: the read address.

Example

The write decoder above

The diagram shows the write logic for a 2-register file with a 1-bit address A and write enable W.

  1. 1.

    L0 = : register 0 loads when W = 1 and A = 0.

  2. 2.

    L1 = : register 1 loads when W = 1 and A = 1.

  3. 3.

    With W = 0, both load enables are 0 and nothing is written.

  4. 4.

    For 8 registers the same pattern gives, for example, L5 = .

Common mistakes

  • Leaving W out of the write logic. A plain decoder would write some register at every edge.

  • Using k address bits for k registers. You need log₂ k.

  • Expecting a read to show the new value during the cycle it is written. It shows the old value until the edge.

Practice Register file

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Registers lesson full course

And 3 more in the Registers lesson.

Basic CPU / Computer Architecture lesson full course

Practice exams

Related terms

Learn it step by step

Register file is taught in Registers and Basic CPU / Computer Architecture.

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