SRAM

Also called: static RAM, static random-access memory, SRAM cell, 6T cell, six-transistor cell

Static RAM: read/write memory that stores each bit in a latch of two cross-coupled inverters. Fast and needs no refresh, but volatile and less dense than DRAM.

SRAM stores each bit in a tiny latch: two inverters wired in a loop, so each holds the other's input. It is the same feedback loop you met in the sr latch. As long as power is on, the loop keeps its value indefinitely, so no refresh is needed. That's what "static" means.

Two access transistors connect the latch to the bit lines when the cell's word line is active. With the four transistors of the two inverters, a typical cell has six transistors (a "6T" cell).

Strengths and weaknesses:

Fast. Reading just senses the latch; nothing has to be restored.
Simple to use. No refresh circuitry.
Large cell. Six transistors take far more area than DRAM's one transistor and one capacitor, so SRAM has lower memory density and costs more per bit.
Volatile. "Static" doesn't mean non-volatile. Power off and the bits are gone.

Where it's used: CPU caches, register files, and the on-chip RAM of microcontrollers: small memories where speed matters most.

Worked examples

Example

SRAM or DRAM?

Pick the better technology for each job.

1.
A 64 KiB cache right next to the processor that must answer in a nanosecond or two: SRAM, for speed.
2.
16 GiB of main memory at a low price: DRAM, for density and cost per bit.
3.
The working RAM inside a small microcontroller, built on the same chip as the CPU: SRAM, since it needs no refresh logic and fits the chip's process.

Example

Counting transistors

How many transistors do the cells of a 32K × 8 SRAM use?

1.
Bits: 32K × 8 = 2¹⁵ × 2³ = 2¹⁸ = 262,144.
2.
At 6 transistors per bit: 1,572,864 transistors, before counting decoders and other support circuits.
3.
A DRAM of the same size would need one transistor (plus a capacitor) per bit: 262,144 transistors.

Common mistakes

Calling SRAM non-volatile. Static means no refresh while powered, not memory without power.
Thinking SRAM is denser than DRAM. Its 6-transistor cell is much larger, so SRAM stores fewer bits per chip.
Thinking SRAM needs refresh. Its latch actively holds the bit; only DRAM leaks.

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