SR latch

Also called: S-R latch, set-reset latch, NOR latch, NOR SR latch, cross-coupled NOR latch, RS latch

A one-bit memory made of two cross-coupled NOR gates: S = 1 sets Q to 1, R = 1 resets it to 0, and S = R = 0 holds the stored value.

The SR latch is the basic memory cell. Two NOR gates are cross-coupled: each gate's output is one of the other gate's inputs. That feedback loop holds a bit, and the two inputs let you change it.

S = 0, R = 0: hold. Q keeps its value.
S = 1, R = 0: set. Q becomes 1.
S = 0, R = 1: reset. Q becomes 0.
S = 1, R = 1: forbidden. Both outputs are forced to 0.

The two outputs are Q and its complement . In the gates, Q = and = .

Why the loop holds: a NOR outputs 1 only when all its inputs are 0. With S = R = 0 and Q = 1, the lower gate sees Q = 1 and outputs = 0; the upper gate then sees two 0s and outputs Q = 1. The value props itself up. Start from Q = 0 and the same reasoning keeps it at 0.

There is no clock. The latch responds as soon as S or R changes, so it is level sensitive. Adding an enable gives the gated sr latch, and steering logic in front gives the gated d latch.

To predict Q at any moment, find the most recent set or reset. Everything since then was a hold.

Worked examples

Example

Tracing set, hold and reset

Q starts at 0. The latch reacts in the slot where S or R changes. Notice the extra set in slot 5 and the extra reset in slot 9.

1.
Slot 1: S = R = 0, hold. Q keeps its starting 0.
2.
Slot 2: S = 1, set. Q = 1.
3.
Slots 3–4: hold. Q stays 1, even though S is back at 0.
4.
Slot 5: S = 1 again. Q is already 1, so nothing visible changes.
5.
Slot 7: R = 1, reset. Q = 0.
6.
Slot 9: R = 1 again. Q is already 0, so it stays 0.

Example

Checking the hold row with the gate equations

Take S = 0, R = 0 and suppose Q = 0. Show that the loop keeps Q = 0.

1.
Lower gate: = = (0 + 0)' = 1.
2.
Upper gate: Q = = (0 + 1)' = 0.
3.
Q = 0 reproduces itself, so the latch is stable at 0.
4.
Repeat with Q = 1: = (0 + 1)' = 0, then Q = (0 + 0)' = 1. Also stable.

Common mistakes

Reading S = R = 0 as "Q = 0". It means hold: keep whatever is stored.
Thinking Q follows S. After S returns to 0, Q stays 1 until R is raised.
Mixing up the NOR and NAND versions. On the NAND latch the inputs are active-low, so 0 is the level that acts.
Applying S = R = 1. Both outputs go to 0, so Q and Q' are no longer complements, and releasing both at once gives an unpredictable result.

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