A basic register overwrites itself at every clock edge. Most registers must instead keep their value for many cycles and change only when told to. The load enable (L, or LD on schematics) is that instruction.
- L = 1 at the edge: the register loads the new data.
- L = 0 at the edge: the register holds its current value.
How it is built: each flip-flop gets a 2:1 multiplexer in front of its D input, with L on the select line. The MUX chooses between two candidates for the next value: keep (the flip-flop's own Q, fed back) or new (the data bit N).
D =
With L = 0 the MUX feeds Q back in, so the flip-flop reloads the value it already has. The clock still reaches every flip-flop at every edge; only what they sample changes. An n-bit register needs n of these 2:1 MUXes.
The tempting alternative, ANDing the clock with L, is called clock gating and should be avoided in hand-built logic: it adds skew and can create false edges.
In a CPU, every register has a load enable, and the control unit's job is to raise the right ones at the right edges. A register transfer such as T1: R2 ← R1 is simply T1 driving R2's load enable.