An arithmetic shift right moves every bit one place toward the LSB, but instead of a 0 it puts a copy of the old sign bit into the MSB. The sign bit ends up duplicated.
Why: in two's complement, a negative number has MSB = 1. Shifting in a 0 (a logical shift right) would make it positive. Copying the sign bit keeps the sign and makes the shift divide by 2 correctly. It is the same idea as sign extension.
1100(−4) →1110(−2) →1111(−1).0110(+6) →0011(+3). For positive numbers it matches a logical shift.
Rounding: the dropped bit is discarded, so the result rounds down, toward −∞, not toward zero. For negative odd numbers this differs from what decimal division might suggest: −5 → −3, and −1 stays −1. See rounding toward negative infinity.
In hardware: a shift-right register with its serial input wired to its own MSB. At the edge, Q3 reloads its old value while Q2 copies it too. A universal shift register in mode 01 with SIR wired to Q3 does exactly this.
There is no separate "arithmetic shift left": shifting left with 0 entering on the right already multiplies a two's complement number by 2, as long as it does not overflow.