Cascading counters

Also called: cascading, cascaded counters, counter cascade, cascade

Chaining small counters into a larger one on a shared clock: the terminal count of each stage drives the enable of the next, like a carry.

To count higher than one counter chip allows, you cascade counters. The rule in a synchronous design:

All the counters share the same clock.
The terminal count output of each counter drives the count enable of the next one up.

The low counter counts every edge. The next counter only counts at edges where the low one is about to wrap, exactly like a carry rippling into the next digit. Each stage then advances once per full cycle of the stages below it.

The modulus of the cascade is the product of the stages' moduli:

two 4-bit binary counters: 16 × 16 = 256, an 8-bit counter;
two BCD decades: 10 × 10 = 100, counting 00 to 99;
a mod-10 units stage and a mod-6 tens stage: 60, a seconds counter.

Because every stage is on the same clock, the result is still a synchronous counter: all the bits change together. The higher stage's TC should include the enable from below, so that pausing the bottom counter pauses everything.

Worked examples

Example

A seconds counter

A units decade (mod-10) and a tens stage (mod-6, counting 0 to 5) share a 1 Hz clock. The units TC drives the tens enable. The display shows 59.

1.
Units at 9 with E = 1, so units TC = 1, enabling the tens stage.
2.
Tens at 5, its last state, so it wraps 5 → 0.
3.
Units wrap 9 → 0.
4.
Display: 00. The pair has 10 × 6 = 60 states, one per second ✓.

Example

Three decades: 199 → 200

Three cascaded BCD counters show 1, 9, 9 (hundreds, tens, units). Each TC is ANDed with that stage's own enable.

1.
Units at 9 → TC = 1 → tens enabled.
2.
Tens at 9 and enabled → its TC = 1 → hundreds enabled.
3.
At the edge: units 9 → 0, tens 9 → 0, hundreds 1 → 2.
4.
Display: 200 ✓.

Common mistakes

Clocking the upper counter from the lower one's TC. That builds a ripple cascade, with its delay and glitches; use the enable instead.
Adding the moduli instead of multiplying them. Two mod-16 counters make mod-256, not mod-32.
Leaving the lower enable out of a middle stage's TC, so the upper stages run while the bottom one is paused.

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