A count enable input E decides, at each clock edge, whether the counter moves:
- E = 1: count, as usual.
- E = 0: hold the present value.
In a synchronous counter built from T flip-flops, you AND E into every T input: T0 = E, T1 = , T2 = , and so on. With E = 0, every T is 0, so every flip-flop holds. With D flip-flops, Dᵢ = Qᵢ ⊕ (E · lower bits all 1).
The clock keeps running the whole time. Enable doesn't stop the clock; it makes every flip-flop choose "hold" at that edge. That matters: gating the clock itself with an AND gate can create short glitchy clock pulses and clock skew, which is why designers use an enable instead. It's the same idea as a register's load enable.
Count enable is also what makes cascading work: the terminal count of one counter drives the enable of the next.