In a synchronous counter, every flip flop is wired to the same clock. Because every bit now sees every edge, the flip-flops can't simply toggle each time. Logic in front of each one decides whether it should toggle at this edge.
With T flip-flops, the toggle rule turns straight into gates. Each T is the AND of all the bits below it:
- T0 = 1
- T1 = Q0
- T2 =
- T3 =
With D flip-flops, D must equal the next value of the bit, so Dᵢ = Qᵢ ⊕ Tᵢ: for example D2 = .
The logic has settled before the edge, and the edge just carries out the decision. So:
- all bits change at the same moment, one tpd after the edge, with no transient states;
- the shortest clock period is tpd + logic delay + setup time, whatever the width (see maximum counter frequency).
The price is extra gates. The counting sequence is identical to a ripple counter's; only the timing differs. Almost all modern counters are synchronous, and adding count enable, parallel load or a synchronous clear is easy because everything happens at the edge.
| T2 | T1 | T0 | |||
|---|---|---|---|---|---|
| 0 | 0 | 0 | 0 | 0 | 1 |
| 0 | 0 | 1 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 | 0 | 1 |
| 0 | 1 | 1 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 | 0 | 1 |
| 1 | 0 | 1 | 0 | 1 | 1 |
| 1 | 1 | 0 | 0 | 0 | 1 |
| 1 | 1 | 1 | 1 | 1 | 1 |