Control signals

Also called: control signal, control lines

The wires from the control unit that tell the datapath what to do each cycle: register loads, mux selects, ALU operation, memory read and write.

The control signals are the control unit's outputs. Each one switches one thing in the datapath. Tiny8 has 12:

Load enables: LdMAR, LdPC, LdMDR, LdIR, LdACC. A register loads at the edge only if its signal is 1.
Mux selects: MARsrc, PCsrc, MDRsrc, ACCsrc. They choose where each register's new value comes from.
ALU: ALUop (0 = add, 1 = subtract).
Memory: Read, Write.

To find the signals for any step written in register transfer notation:

Every register on the left of an arrow gets its load signal (or Write, if the destination is memory).
Set each of those registers' mux to the source on the right.
If the source is memory, assert Read. If it's the ALU, set ALUop.
Every other load, Read and Write is 0.

The 0s matter: an extra LdPC skips an instruction, and an extra Write corrupts memory. But a mux select only matters when its register loads, so otherwise it's a don't-care.

Worked examples

Example

Signals across a LOAD

The diagram shows six Tiny8 control signals during one LOAD, one slot per step: F1, F2, F3, D, E1, E2.

1.
F1 MAR ← PC: LdMAR = 1, with MARsrc = 0 to pick the PC.
2.
F2 MDR ← M[MAR], PC ← PC + 1: Read, LdMDR and LdPC are all 1.
3.
F3 IR ← MDR: only LdIR.
4.
D MAR ← IR[3:0]: LdMAR again, with MARsrc = 1.
5.
E1 MDR ← M[MAR]: Read and LdMDR.
6.
E2 ACC ← MDR: LdACC, with ACCsrc = 0 to pick the MDR.

Example

Signals for SUB's last step

Find the signals for E2 of SUB: ACC ← ACC − MDR.

1.
Destination: ACC, so LdACC = 1.
2.
Source: the ALU, so ACCsrc = 1 and ALUop = 1 (subtract).
3.
No memory access: Read = Write = 0. All other loads are 0.

Common mistakes

Asserting a load for a register on the right of an arrow. Sources are read, not loaded.
Treating a stray load enable as harmless. It overwrites that register.
Worrying about a mux select in a step where its register doesn't load. It's a don't-care.

Practice Control signals

Interactive questions with instant feedback and a worked solution for every wrong answer.

Memory lesson full course

And 1 more in the Memory lesson.

Basic CPU / Computer Architecture lesson full course

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Practice exams

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Control signals is taught in Basic CPU / Computer Architecture.

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