DRAM refresh

Also called: refresh, memory refresh, refresh cycle, refreshing DRAM

The periodic reading and rewriting of every DRAM cell, row by row, to restore the charge that leaks from its capacitors before the data is lost.

A DRAM cell holds a bit as charge on a tiny capacitor, and that charge leaks away within milliseconds. Refresh is the fix: before the charge fades too far, the chip reads each cell and writes the value back at full strength.

How it's done:

Cells are refreshed a whole row at a time. Activating a row's word line senses every cell in the row and restores them together.
Every row must be refreshed within a fixed period, commonly 64 ms.
The memory controller (or the chip itself) issues refresh commands spread evenly through that period.

Refresh has a cost: while a row is being refreshed, it can't serve normal reads and writes, so a small fraction of the memory's time goes to housekeeping.

Refresh happens only while the chip is powered. It keeps the data alive during operation, but it can't save it from a power cut: DRAM is still volatile.

SRAM needs no refresh at all. Its latch actively holds each bit, which is what "static" means.

Worked example

Example

Refresh rate

A DRAM has 16,384 rows that must all be refreshed every 64 ms.

1.
64 ms ÷ 16,384 = 0.00390625 ms.
2.
About one row every 3.9 µs.
3.
Doubling the rows halves the time available per row.

Common mistakes

Thinking refresh lets DRAM survive power-off. It only works while powered; DRAM is volatile.
Thinking SRAM needs refresh too. Only DRAM's capacitors leak.
Refreshing bit by bit. Refresh restores a whole row at once.

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