Gated SR latch

Also called: clocked SR latch, SR latch with enable, enabled SR latch, gated S-R latch

An SR latch with an enable input: S and R only reach the latch while the enable is 1. With the enable at 0, the latch holds.

A gated SR latch adds an enable E to the basic SR latch. Two AND gates sit in front, so the inner latch sees and .

E = 0: both inner inputs are 0, so the latch holds, whatever S and R do.
E = 1: the latch behaves like a plain SR latch: set, reset or hold.

This lets you choose when the latch may change. The enable is often driven by a clock, which is why it is sometimes called a clocked SR latch. It is still level sensitive: while E = 1, every change on S or R shows through immediately.

It keeps the SR latch's forbidden input: with E = 1, S = R = 1 forces both outputs to 0.

The gated D latch is the fix. Drive S with D and R with , so the inner signals become and . They can never both be 1, and there is now just one data input.

A gated SR latch's next state is Q⁺ = , valid when S and R are never both 1 while E = 1.

Worked example

Example

Tracing a gated SR latch

Q starts at 0. The diagram above shows the gating; the inner SR latch is not drawn.

1.
Slot 1: E = 0, so S = 1 is blocked. Q holds 0.
2.
Slot 2: E = 1 and S = 1: set. Q = 1.
3.
Slot 3: E = 1, S = R = 0: hold.
4.
Slots 4–5: E = 0, so R = 1 is blocked. Q stays 1.
5.
Slot 6: E = 1 and R = 1: reset. Q = 0.
6.
Slot 8: E = 0 blocks S. Q stays 0.

Common mistakes

Thinking E = 0 clears the latch. It holds.
Thinking the enable makes it edge-triggered. It is still a level-sensitive latch.
Assuming the enable removes the forbidden input. S = R = 1 with E = 1 is still forbidden.