Forbidden state

Also called: forbidden input, invalid state, invalid input, not-allowed state, illegal input, forbidden combination

The input combination an SR latch must never receive, S = R = 1 (or S' = R' = 0 on a NAND latch), which breaks the Q and Q' relationship.

The forbidden state is the input combination that an SR latch is not designed to handle: S = 1 and R = 1 together. On a NAND SR latch it is = = 0.

What goes wrong:

While it is applied, both outputs are forced to the same value: both 0 on a NOR latch, both 1 on a NAND latch. Q and are no longer complements, so the latch is not storing a sensible bit.
When it is released, the outcome depends on how. If one input drops first, the latch passes through an ordinary set or reset, and the input that stayed active longer wins. If both drop at exactly the same moment, the two gates both try to switch, and whichever is a hair faster decides Q. That is a race, and the result is unpredictable.

How designers deal with it:

Simply never apply it to a bare SR latch.
Build circuits where it cannot happen. The gated D latch drives S = and R = , which are never both 1.
Give the combination a useful meaning instead. The JK flip-flop turns J = K = 1 into toggle.

The same rule applies to asserting a flip-flop's preset and clear at once.

Worked examples

Example

Entering and leaving S = R = 1 safely

A NOR SR latch starts with Q = 0. Watch both outputs as S = R = 1 is applied, then R is released first.

1.
Slot 1: hold. Q = 0, Q' = 1.
2.
Slot 2: set. Q = 1, Q' = 0.
3.
Slot 3: S = R = 1. Both NOR gates see a 1, so Q = 0 and Q' = 0. Not complements.
4.
Slot 4: R drops while S stays 1. That is a plain set: Q = 1, Q' = 0.
5.
Slot 5: hold at 1. The input that stayed high longer (S) won.

Example

Why a D latch has no forbidden input

Inside a gated D latch, S = and R = . Can both be 1?

1.
S = 1 needs D = 1 and E = 1.
2.
R = 1 needs D = 0 and E = 1.
3.
D cannot be 0 and 1 at once, so S and R are never both 1.

Common mistakes

Calling J = K = 1 forbidden on a JK flip-flop. There it means toggle.
Saying S = R = 1 always gives a random Q. While applied, the outputs are predictable (both 0 on a NOR latch); the risk is when both inputs are released together.
Using the NOR result for a NAND latch. NAND forces both outputs to 1.

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