A level-sensitive storage element pays attention for as long as its enable sits at the active level. During that time it is transparent: its output follows its input, change for change. When the enable leaves the active level, the output freezes.
Every latch is level-sensitive:
- An SR latch responds whenever S or R is active; it has no enable at all.
- A gated D latch is transparent while EN = 1 (or while EN = 0 if it has a bubble on EN) and holds otherwise.
The contrast is edge triggered, where the device acts only at the instant the clock changes. See latch vs flip flop.
Why you care: transparency is handy (a latch passes data through with no waiting), but it is risky in clocked systems. If two level-sensitive stages are open at the same time, data can race through both in one enable pulse, and how far it gets depends on how long the enable stays high. Edge-triggered flip-flops remove that uncertainty.
Tracing tip: split the waveform into active stretches and inactive stretches. In an active stretch, copy the input slot by slot. In an inactive stretch, copy the previous slot.