Hold fix

Also called: buffer insertion, delay buffer insertion, padding the short path

Repairing a hold violation by adding delay, usually buffers, to the short path so new data arrives after the hold window closes.

A hold violation means new data reaches the capturing flip-flop too early. Changing the clock period can't help, because the hold constraint has no period in it. The fix is to make the fast path slower: add delay to the short path, usually by inserting buffers (or pairs of inverters) into the wire.

The recipe:

Find the shortfall: it's the negative hold slack, th − (tcq(min) + tcd).
Add at least that much contamination delay to the failing path.
Recheck setup. The buffers also add tpd to that path, which might now break the setup constraint.

The paths most likely to need a hold fix are the ones with little or no logic, such as a direct flip-flop-to-flip-flop link in a shift register. Paths with plenty of logic usually have enough tcd already.

Don't add delay everywhere: only the paths that fail hold need it, and extra delay elsewhere just eats into setup slack.

Worked example

Example

Sizing a buffer

A shift register stage wires Q straight to D. The flip-flops have tcq(min) = 25 ps, tcq = 70 ps, th = 60 ps and tsu = 40 ps. The clock period is 500 ps.

1.
Hold: 25 + 0 − 60 = −35 ps. It fails by 35 ps.
2.
Add a buffer with tcd ≥ 35 ps. Say it has tcd = 35 ps and tpd = 60 ps.
3.
New hold slack: 25 + 35 − 60 = 0 ps. It just passes.
4.
Recheck setup: 70 + 60 + 40 = 170 ps ≤ 500 ps. Still fine.

Common mistakes

Slowing the clock to fix hold. It has no effect.
Adding delay to the critical path. The short path is the one failing.
Forgetting to recheck setup after adding buffers.

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Hold fix is taught in Timing and Sequential Logic.

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