Hold constraint

Also called: hold check, min-delay constraint, hold time constraint, hold violation, race condition

The rule that new data launched at a clock edge must not reach the next flip-flop before its hold time ends: tcq(min) + tcd ≥ th.

The same clock edge does two things on a register to register path. The capturing flip-flop locks in its current D value, and the launching flip-flop sends out new data. The capturing flip-flop needs its D held steady for the hold time th after the edge. If the new data races through too quickly, it overwrites the value being captured.

The earliest the new data can arrive is the minimum clock to q delay plus the logic's contamination delay on the short path. So:

tcq(min) + tcd ≥ th

This check uses minimum delays, because the fastest data is the danger. The margin is the hold slack: tcq(min) + tcd − th.

Notice there's no clock period in it. Both events happen at the same edge, so the race doesn't care when the next edge comes. That makes a hold violation nasty: slowing the clock can't fix it, and the chip fails at every frequency. The fix is a hold fix: add delay, such as buffers, to the short path, then recheck setup.

With clock skew, the rule becomes tcq(min) + tcd ≥ th + tskew.

Worked examples

Example

A failing hold check

A path has tcq(min) = 35 ps and a short path through the logic with tcd = 10 ps. The flip-flops need th = 60 ps.

1.
Earliest arrival of new data: 35 + 10 = 45 ps after the edge.
2.
Required: no earlier than th = 60 ps.
3.
Hold slack = 45 − 60 = −15 ps: a hold violation.
4.
Slowing the clock won't help. Add at least 15 ps of contamination delay to that short path.

Example

A passing hold check

Another path has tcq(min) = 45 ps, tcd = 30 ps and th = 55 ps.

1.
Earliest arrival: 45 + 30 = 75 ps.
2.
75 ≥ 55, so it passes. Hold slack = +20 ps.
3.
The clock period never entered the working, and it never does in a hold check.

Common mistakes

Including the clock period T. If T appears in your hold working, you've mixed it up with setup.
Using maximum delays (tcq, tpd). Hold needs the earliest data, so it uses tcq(min) and tcd.
Using the critical path. The short path, with the smallest tcd, is the one that can fail hold.
Trying to fix a hold violation by slowing the clock.

Practice Hold constraint

Interactive questions with instant feedback and a worked solution for every wrong answer.

Timing and Sequential Logic lesson full course

And 4 more in the Timing and Sequential Logic lesson.

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Learn it step by step

Hold constraint is taught in Timing and Sequential Logic.

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