Setup constraint

Also called: setup check, max-delay constraint, setup time constraint

The rule that the clock period must cover tcq + tpd + tsu on every register-to-register path, so data arrives in time for the next edge.

Picture a register to register path: a launching flip-flop, some logic, and a capturing flip-flop on the same clock. At one edge, new data leaves the launching flip-flop. It must reach the capturing flip-flop and be stable tsu before the next edge.

In the worst case the data:

leaves the flip-flop after the clock to q delay tcq,
spends the critical path delay tpd in the logic,
must then be steady for the setup time tsu.

So the period must satisfy:

T ≥ tcq + tpd + tsu

The smallest legal period is the minimum clock period Tmin = tcq + tpd + tsu, and the fastest clock is fmax = 1 / Tmin. Every path on the chip must pass, so the slowest path sets the clock for everything.

This check uses maximum delays, because the latest-arriving data is the danger. If a path fails, you have a setup violation. You can fix it by slowing the clock, speeding up the logic, or pipelining it. With clock skew, the rule becomes T ≥ tcq + tpd + tsu − tskew.

Worked examples

Example

Fastest clock for one path

A path has tcq = 80 ps, logic tpd = 650 ps and tsu = 70 ps. Find Tmin and fmax.

1.
Add the three terms: 80 + 650 + 70 = 800 ps.
2.
Tmin = 800 ps = 0.8 ns.
3.
fmax = 1 ÷ 0.8 ns = 1.25 GHz (or 1000 ÷ 0.8 = 1250 MHz).

Example

How much logic fits?

A design must run at 400 MHz. Its flip-flops have tcq = 0.3 ns and tsu = 0.2 ns. What's the largest logic delay allowed?

1.
Period: T = 1000 ÷ 400 = 2.5 ns.
2.
Rearrange: tpd ≤ T − tcq − tsu.
3.
2.5 − 0.3 − 0.2 = 2.0 ns.
4.
Any path whose logic takes longer than 2.0 ns fails setup at 400 MHz.

Common mistakes

Dropping tcq or tsu and timing the logic alone. That gives a clock that's too fast.
Using contamination delays. Setup is about the slowest data, so it uses tpd.
Checking only one path. The slowest register-to-register path sets the clock.

Practice Setup constraint

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Timing and Sequential Logic lesson full course

And 10 more in the Timing and Sequential Logic lesson.

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Learn it step by step

Setup constraint is taught in Timing and Sequential Logic.

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