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Load immediate (LDI)

Also called: immediate operand, immediate addressing, immediate value

An instruction whose operand is a constant inside the instruction itself, not a memory address. LDI k puts the number k in the accumulator.

Most Tiny8 instructions name an address, and the CPU reads the operand from memory. An immediate operand is different: the value is inside the instruction word itself. LDI k (load immediate) puts the number k straight into the ACC.

The course builds LDI as an extension, using the spare opcode 7, so 7k means LDI k. Adding it follows the usual recipe:

  1. RTN: after fetch and decode, E1: ACC ← IR[3:0], with four 0s added on top to make 8 bits. Z loads with the ACC.
  2. Datapath: there's no path from IR[3:0] to the ACC, so the ACC's mux gets a third input. A 3-input mux needs a 2-bit select, so ACCsrc becomes two bits.
  3. Control: one execute step, so LDI goes from E1 straight back to F1. LdACC gains an "E1 and LDI" term.

LDI takes 5 cycles, one fewer than LOAD, and saves storing small constants in memory. The cost: k is only 4 bits, so it can only load 0 to 15.

Worked example

Example

A program with LDI

Tiny8 + LDI runs: 0: LDI 6 (76), 1: SUB E (4E), 2: SUB E (4E), 3: STORE F (2F), 4: HALT (00). M[E] = 2.

  1. 1.

    LDI 6: ACC = 6 (from the instruction, not from memory), Z = 0. 5 cycles.

  2. 2.

    SUB E twice: ACC = 6 − 2 − 2 = 2. 6 cycles each.

  3. 3.

    STORE F: M[F] = 2. 6 cycles.

  4. 4.

    HALT: 5 cycles. Total 5 + 6 + 6 + 6 + 5 = 28 cycles. With LOAD instead of LDI it would be 29, plus a memory word for the constant.

Common mistakes

  • Treating k as an address. LDI 3 loads the number 3, not M[3].

  • Asserting Read in LDI's execute step. Nothing is read from memory.

  • Forgetting that the wider mux select changes the control equations for the old instructions' ACCsrc too.

Practice Load immediate (LDI)

Interactive questions with instant feedback and a worked solution for every wrong answer.

Learn it step by step

Load immediate (LDI) is taught in Basic CPU / Computer Architecture.