Multi-cycle processor

Also called: multi-cycle, multicycle, multi-cycle CPU, multi cycle, multi-cycle datapath

A CPU that runs each instruction as several short clock cycles, one step per cycle, so it can reuse hardware and use a fast clock.

A multi-cycle processor breaks each instruction into steps and does one step per clock cycle. Tiny8 is one: fetch takes three cycles (F1, F2, F3), decode one (D), and execute one or two (E1, E2).

What follows:

CPI > 1. Tiny8's memory instructions take 6 cycles; jumps and HALT take 5.
Short period. The clock only has to fit the slowest step, not the slowest whole instruction.
Simple instructions finish sooner. A JMP doesn't wait through steps it doesn't need.
Hardware reuse. One memory serves both the instruction fetch and the data access, because they happen in different cycles. One ALU can do different jobs in different steps.
More control. The control unit needs a state per step, and intermediate results need registers (like the MDR and IR) to hold them between cycles.

Compared with a single cycle processor, neither is always faster. Compute cpu execution time for both: a multi-cycle CPU wins when its period is short enough to make up for its higher CPI.

Worked example

Example

Counting cycles in Tiny8

A Tiny8 program runs LOAD, ADD, STORE, JMP, then LOAD, STORE, HALT.

1.
Memory instructions: LOAD, ADD, STORE, LOAD, STORE = 5 × 6 = 30 cycles.
2.
JMP and HALT: 2 × 5 = 10 cycles.
3.
Total: 40 cycles. CPI = 40 ÷ 7 ≈ 5.71.
4.
At 100 MHz (10 ns per cycle), that's 400 ns.

Common mistakes

Saying a multi-cycle CPU is always faster because its steps are short. Its CPI is higher too.
Thinking it needs separate instruction and data memories. Reusing one memory is a main benefit.

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