Skip to content
BetterDL

Result multiplexer

Also called: result MUX, ALU result MUX, ALU output multiplexer

The multiplexer at an ALU's output that passes through the result of the operation chosen by the opcode. Every unit computes; the MUX selects one.

Inside an ALU, every functional unit (adder, AND, OR, …) computes its answer all the time. The result multiplexer decides which one becomes the output Y.

It's an ordinary multiplexer whose data inputs are the units' outputs and whose select lines are the function select bits. In the course's 2-operation slice, a 2:1 MUX with select F0 gives:

Y =

So F0 = 0 passes the AND result and F0 = 1 passes the OR result.

With the 2-bit opcode F1F0 (AND, OR, ADD, SUB) there are three units to choose from. ADD and SUB both select the adder's sum, so the course's slice uses F1 alone for that case: Y = , where S is the adder's sum.

Why compute everything and then select? It's simple and fast: no unit has to wait to be told to start. The cost is wasted switching power, which real processors reduce in other ways.

The MUX output is the ALU's real result, so the N and Z status flags must be taken after it.

F0ABY

Worked example

Example

Tracing the 2:1 result MUX

A = 1, B = 0, in the AND/OR slice.

  1. 1.

    The AND gate outputs 0 and the OR gate outputs 1, whatever F0 is.

  2. 2.

    F0 = 0: Y = 1·1·0 + 0·(1 + 0) = 0, the AND result.

  3. 3.

    F0 = 1: Y = 0·1·0 + 1·(1 + 0) = 1, the OR result.

Common mistakes

  • Thinking the unselected units are switched off. They still compute.

  • Taking N and Z from before the MUX.

  • Merging the unit outputs with a plain OR instead of a MUX, which mixes results together.

Practice Result multiplexer

Interactive questions with instant feedback and a worked solution for every wrong answer.

Adders and ALUs lesson full course

Practice exams

Related terms

Learn it step by step

Result multiplexer is taught in Adders and ALUs.

Adders and ALUs →

All terms