A rising edge is a 0 → 1 transition: the instant a signal goes from low to high. On a waveform it is the upward step.
Rising edges matter most on the clock. A positive-edge-triggered flip flop samples its inputs at each rising clock edge and holds its output in between. Unless a question says otherwise, every flip-flop in this course is positive-edge-triggered. The opposite transition is the falling edge.
Finding rising edges on a slotted timing diagram:
- Look for a slot where the signal is 1 and the slot before it is 0. That slot holds the edge.
- A long high stretch contains only one rising edge, at its start.
- A signal that starts at 1 has no rising edge in its first slot, because there was no 0 before it.
In this course's diagrams, a flip-flop's Q changes in the same slot as the rising edge, using the input value in that slot. Inputs never change exactly at an edge, so that value equals the one just before the edge.
A clock with period T has one rising edge per period, so a 100 MHz clock has 100 million rising edges per second.