Timing diagram

Also called: waveform, waveforms, timing chart, waveform diagram, timing waveform

A picture of digital signals over time: each signal is a line that is high for 1 and low for 0, with time running left to right.

A timing diagram (or waveform) shows how signals change over time. It is the natural way to describe real hardware, where inputs switch on and off while a circuit runs.

How to read one:

Time runs left to right.
Each row is one signal, named on the left.
A line drawn high means 1; a line drawn low means 0. These are the two logic levels.
The grid divides time into equal slots, counted from the left.
A vertical step marks a change: low to high is a rising edge, high to low a falling edge.

For a gate or a combinational circuit, each slot is just one row of the truth table. Read straight down a slot, note the inputs, look up the output, and write it under the same slot. Then move one slot right and repeat, even if nothing changed.

Real gates take a moment to respond, called propagation delay, so a measured output lags slightly behind its inputs. In a first course the delay is ignored and the output changes in the same slot. Later, timing diagrams are how you study delays, glitches and clocked circuits like flip-flops.

To name an unknown 2-input gate from a waveform, find one slot for each of 00, 01, 10 and 11, read Y in each, and match the column to a known gate.

Worked examples

Example

Drawing a NOR output

A and B drive a 2-input NOR gate. Find Y in each of the 8 slots. NOR is 1 only when both inputs are 0.

1.
Slot 1: A = 0, B = 0. Both low, so Y = 1.
2.
Slot 2: A = 1, B = 0. Y = 0.
3.
Slot 3: A = 1, B = 1. Y = 0.
4.
Slot 4: A = 0, B = 1. Y = 0.
5.
Slot 5: A = 0, B = 0. Both low again, so Y = 1.
6.
Slots 6 to 8: (1, 1), (0, 1) and (1, 0). At least one input is high in each, so Y = 0.
7.
Y = 1 0 0 0 1 0 0 0.

Example

Naming a gate from its waveform

A single 2-input gate produced Y. Which gate is it?

1.
Find each input combination: slot 1 is 00, slot 2 is 10, slot 3 is 11 and slot 4 is 01.
2.
Read Y in those slots: 00 → 1, 01 → 1, 10 → 1, 11 → 0.
3.
The column 1 1 1 0 is NAND.
4.
Check the rest: slot 5 is 11 with Y = 0 and slot 6 is 00 with Y = 1. Both agree.

Common mistakes

Counting a long flat stretch as one value. A line that stays high for three slots is three 1s.
Reading A in one slot and B in the next. Keep your eye on a single vertical column.
Shifting the output one slot right. With delay ignored, Y goes directly under the inputs that produced it.
Naming a gate when one input combination never appears. Without all four rows, more than one gate may fit.

Practice Timing diagram

Interactive questions with instant feedback and a worked solution for every wrong answer.

Logic Gates lesson

And 8 more in the Logic Gates lesson.

Adders and ALUs lesson full course

Latches and Flip-Flops lesson full course

And 19 more in the Latches and Flip-Flops lesson.

Registers lesson full course

Counters lesson full course

Memory lesson full course

E is an active-high chip select and R is the read/write line (1 = read). Draw Drive, which is 1 whenever the chip is putting a word on the data lines.

Timing and Sequential Logic lesson full course

Basic CPU / Computer Architecture lesson full course

Slots 0–5 are the steps of a LOAD (F1, F2, F3, D, E1, E2); slots 6–10 are the steps of the JMP after it (F1, F2, F3, D, E1). M is the decoder output "the instruction in IR is LOAD,…

Practice exams

Learn it step by step

Timing diagram is taught in Logic Gates, Latches and Flip-Flops and Timing and Sequential Logic.

Logic Gates →Latches and Flip-Flops →Timing and Sequential Logic →

All terms