Asynchronous (ripple) counter

Also called: ripple counter, asynchronous counter, async counter, ripple up counter

A counter in which only the first flip-flop sees the system clock; each later flip-flop is clocked by the stage before it, so changes ripple through.

A ripple counter is the cheapest way to build a counter. Every stage is a t flip flop with T = 1 (or a JK with J = K = 1), so it toggles at every clock edge it receives. The trick is in the wiring:

Only the first flip-flop, Q0, gets the system clock.
Each later flip-flop is clocked by the output of the stage below it.

No gates are needed. Instead of logic deciding whether a bit should toggle, the circuit only delivers a clock edge to a bit when it ought to toggle.

By the toggle rule, bit k must toggle when bit k − 1 falls from 1 to 0 (that is when a carry reaches it). With positive-edge flip-flops, which this course uses unless told otherwise, you get that edge by clocking each stage from the previous stage's : rises exactly when Q falls.

It is called asynchronous because the flip-flops don't share one clock, and ripple because each change travels up the chain one stage at a time. That has two costs:

Ripple delay: the last bit can settle as late as n × tpd after the edge.
Transient states: while the change ripples, the outputs briefly show wrong counts.

A synchronous counter fixes both by giving every flip-flop the same clock.

Worked examples

Example

The chain reaction for 011 → 100

A 3-bit ripple counter of positive-edge T flip-flops (T = 1), each stage clocked from the previous , holds 011. Follow one clock edge up the chain.

1.
CLK rises, so Q0 toggles 1 → 0. Outputs now read 010.
2.
Q0 fell, so rose: that clocks Q1, which toggles 1 → 0. Outputs read 000.
3.
Q1 fell, so rose: that clocks Q2, which toggles 0 → 1. Outputs read 100.
4.
Q2 rose, so fell: nothing further. The count settles at 100 = 4 ✓.

Example

Which edges reach which stage?

Same counter, from 000 over the first four clock edges. A stage only moves when the one below it falls.

1.
Edge 1: Q0 rises 0 → 1. A rise doesn't clock Q1. Count 001.
2.
Edge 2: Q0 falls, clocking Q1 (0 → 1). Q1 rose, so Q2 is not clocked. Count 010.
3.
Edge 3: Q0 rises. Count 011.
4.
Edge 4: Q0 falls → Q1 falls → Q2 rises. Count 100. Only this edge traveled all the way up.

Common mistakes

Clocking positive-edge stages from Q instead of . That makes each stage toggle when the one below rises, which counts down.
Assuming all the bits change together. They change one after another, a tpd apart, so the outputs pass through wrong values first.
Thinking asynchronous means there is no clock. Q0 is clocked normally; only the later stages take their clock from another flip-flop.

Practice Asynchronous (ripple) counter

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Asynchronous (ripple) counter is taught in Counters.

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