An asynchronous clear (CLR) forces Q to 0 right away. It does not wait for a clock edge and it overrides everything else: the clock, the data inputs and any load enable.
In a register, the clear pins of all the flip-flops are tied together, so one signal resets the whole word to 0 at once.
Why use it:
- At power-up, flip-flops wake with random values. An asynchronous clear sets a known state even before the clock has started. See power on reset.
- A clear can never be missed: even a short pulse between clock edges takes effect.
It is often active-low, written with a bubble or as . Then the pin sits at 1 in normal use and is pulled to 0 to clear.
Compare the synchronous clear, which is ordinary logic in front of D and only takes effect at the next clock edge. Both end with Q = 0; the difference is when.
The partner pin is the asynchronous preset, which forces Q to 1. Never assert both together.
One caution: because it ignores the clock, releasing an asynchronous clear right next to a clock edge can cause timing problems. Large designs often release reset through a synchronizer so every flip-flop leaves reset on the same edge.