Ripple delay

Also called: ripple counter delay, settling time, cumulative delay, ripple settling time

The total settling time of a ripple counter: each stage waits for the one below it, so in the worst case the last bit settles n × tpd after the edge.

In an asynchronous (ripple) counter, a stage can't start changing until the stage below it has changed and handed it a clock edge. Each flip-flop adds its own propagation delay (tpd), so the delays stack up like dominoes.

If only Q0 changes (say 0110 → 0111), the count settles after 1 × tpd.
If every bit changes (0111 → 1000, or 1111 → 0000), the change has to pass through all n stages. The last bit settles n × tpd after the edge. That's the worst case, and the one that sets the speed limit.

Two consequences follow:

The clock period must be at least n × tpd (plus the delay of any logic reading the count), so the maximum counter frequency is at most 1 / (n × tpd). Adding bits slows the counter down.
Until the ripple finishes, the outputs show transient states, which can make decoding logic glitch.

A synchronous counter avoids ripple delay entirely: every bit changes one tpd after the shared clock edge, however wide the counter is.

Worked examples

Example

Watching 0111 become 1000

A 4-bit ripple counter has tpd = 12 ns per flip-flop. The clock edge arrives at t = 0 while it holds Q3Q2Q1Q0 = 0111.

1.
t = 12 ns: Q0 falls 1 → 0. Outputs read 0110.
2.
t = 24 ns: Q1 falls 1 → 0. Outputs read 0100.
3.
t = 36 ns: Q2 falls 1 → 0. Outputs read 0000.
4.
t = 48 ns: Q3 rises 0 → 1. Outputs read 1000 and the count has settled.
5.
Total: 4 × 12 = 48 ns. The clock period must be at least 48 ns, so the clock can't exceed 1 / 48 ns ≈ 20.8 MHz.

Example

How many stages fit in a period?

Ripple flip-flops have tpd = 8 ns and the clock runs at 10 MHz. What is the widest ripple counter that settles before every edge?

1.
The period is 1 / 10 MHz = 100 ns.
2.
Each stage costs 8 ns, so n × 8 ≤ 100 → n ≤ 12.5.
3.
Round down: 12 stages.

Common mistakes

Using (n − 1) × tpd. Q0 also takes a tpd after the clock edge, so the last of n stages settles after n × tpd.
Thinking every edge costs n × tpd. Most edges change only a few bits; n × tpd is the worst case, which is the one that limits the clock.
Applying ripple delay to a synchronous counter. There, all bits change together one tpd after the edge.

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