In an asynchronous (ripple) counter the bits don't change together. Each one changes a tpd after the one below it. So between the clock edge and the moment the count settles, the outputs spell out wrong counts. Those brief wrong values are transient states.
For 011 → 100, a ripple counter actually shows 011 → 010 → 000 → 100. The values 010 and 000 exist for about one tpd each.
Why care? Logic that decodes the count sees them too. A gate looking for 000 will put out a short glitch even though the counter only passed from 3 to 4. If that gate drives a clear, a load or an interrupt, the circuit misbehaves.
Fixes:
- Use a synchronous counter: all bits change together, so there are no transient states.
- Sample the decoded output with a flip-flop on the opposite clock edge, half a period later, when the count has settled.
- Only read the count after the worst-case ripple delay.
The same term covers the brief state N that shows up in a mod-N counter with an asynchronous clear: it exists only until the clear takes effect.