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Clock domain crossing

Also called: CDC, clock domain

A signal passing from logic on one clock to logic on another, unrelated clock. To the receiver it is asynchronous and must be synchronized.

A clock domain is the set of flip-flops driven by one clock. Big chips have many: a CPU core, a USB controller and a display controller may each run at their own frequency. A clock domain crossing is any signal that leaves one domain and is read by another.

To the receiving domain, the signal is an asynchronous input. Its changes are timed by the sender's clock, so they can land anywhere relative to the receiver's edges, including inside a setup and hold window. That risks metastability.

The standard tools:

  • Single bits (a flag, a request line) go through a two flip flop synchronizer clocked by the receiver.
  • Multi-bit values can't be synchronized bit by bit, because the bits may settle on different cycles and produce a value that never existed. They need handshakes, Gray-coded counters or FIFOs, which go beyond this course.

The ordinary setup and hold checks don't apply across a crossing, because the two clocks have no fixed relationship.

Worked example

Example

Crossing a 'done' flag

A 50 MHz block raises a one-bit 'done' flag that a 120 MHz block must read.

  1. 1.

    The two clocks are unrelated, so 'done' can change at any point in the 120 MHz cycle.

  2. 2.

    Pass it through two flip-flops clocked at 120 MHz. The first may go metastable; the second sees a clean value.

  3. 3.

    The receiver sees 'done' one or two of its cycles late (about 8.3 to 16.7 ns at 120 MHz). That latency is the price of safety.

Common mistakes

  • Running a normal setup check between unrelated clocks. There's no fixed period between their edges.

  • Synchronizing a multi-bit bus one bit at a time.

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Related terms

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Clock domain crossing is taught in Timing and Sequential Logic.

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