Often you want a register to load new data on some clock cycles and hold its value on others. A clock enable does this the safe way:
- the clock goes straight to the flip-flop, untouched;
- a 2-to-1 multiplexer in front of D chooses the next value.
With enable E, new data N and current output Q:
D =
When E = 1, D = N and the flip-flop loads. When E = 0, D = Q and the flip-flop reloads its own value, so it appears to hold.
It's the same idea as a register's load enable. The name "clock enable" is common in FPGA flip-flops, which often have a CE pin built in.
Why not just gate the clock? A gated clock lets glitches on the enable become false clock edges and adds clock skew. The mux version keeps every flip-flop on the same clean clock, so synchronous design timing checks still apply.
| D | |||
|---|---|---|---|
| 0 | 0 | 0 | 0 |
| 0 | 0 | 1 | 1 |
| 0 | 1 | 0 | 0 |
| 0 | 1 | 1 | 1 |
| 1 | 0 | 0 | 0 |
| 1 | 0 | 1 | 0 |
| 1 | 1 | 0 | 1 |
| 1 | 1 | 1 | 1 |