Two-flip-flop synchronizer

Also called: synchronizer, 2-FF synchronizer, double flopping, double-flop synchronizer, brute-force synchronizer

Two flip-flops in series on the receiving clock that an asynchronous input passes through, giving any metastability a full cycle to settle.

An asynchronous input will sometimes change inside a flip-flop's setup-and-hold window, so the first flip-flop to sample it may go metastable. A two-flip-flop synchronizer contains the damage:

The raw input goes into flip-flop S1, clocked by the receiving clock.
S1's output goes straight into flip-flop S2, on the same clock. No logic in between.
The rest of the circuit reads only S2.

If S1 goes metastable, it has almost a whole clock period to settle before S2 samples it. Because the chance of still being unsettled shrinks exponentially with time, S2 almost always sees a clean 0 or 1.

What it costs and what it doesn't promise:

Latency: the circuit sees the input one or two cycles later than it arrived.
Not perfect: failure becomes extremely rare, not impossible. More stages or a slower clock make it rarer still.
One bit only: synchronizing each bit of a multi-bit value separately can produce a value that never existed, because bits may settle on different cycles.

Synchronize an input once, then fan the synchronized signal out. Never send the raw input to several flip-flops.

Worked example

Example

Following a button press through

In the diagram, the clock rises in slots 2, 4, 6, 8 and 10. The button input IN rises in slot 3, between edges.

1.
Slot 4 edge: S1 samples IN = 1, so S1 becomes 1. S2 samples S1's old value, 0.
2.
Slot 6 edge: S2 samples S1 = 1, so S2 becomes 1. The rest of the circuit now sees the press.
3.
Here IN changed well clear of an edge, so nothing went metastable. If IN had risen right at the slot 4 edge, S1 might have hovered. It would then have most of a period to settle before S2 sampled it at slot 6.
4.
If S1 settled to 0 in that case, it would catch the still-held button at slot 6, and S2 would show it at slot 8. Either way S2 shows a clean value.

Common mistakes

Putting logic between the two flip-flops. It eats into the settling time.
Feeding the raw input to several flip-flops. They may disagree; synchronize once, then fan out.
Saying the synchronizer removes metastability. It only makes failures very rare.
Synchronizing a multi-bit bus bit by bit.

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