Setup-and-hold window

Also called: setup and hold window, aperture, aperture time, sampling window

The interval from tsu before to th after a clock edge during which a flip-flop's D input must not change. Its width is tsu + th.

A flip-flop doesn't sample D at a single instant. It needs D steady across a short window around the clock edge:

it opens tsu before the edge (the setup time),
it closes th after the edge (the hold time),
so its width is tsu + th.

Think of a camera with a slow shutter: the subject has to hold still for the whole exposure, not just the moment the button clicks. Outside the window D can do anything; the flip-flop ignores it.

If D changes inside the window, the flip-flop may capture the wrong value or go metastable. The setup constraint keeps data from arriving too late, at the start of the window. The hold constraint keeps new data from arriving too early, before the window has closed.

An asynchronous input has no fixed timing, so sooner or later it will land inside the window. That's why it needs a synchronizer.

Worked example

Example

Window width and position

A flip-flop has tsu = 90 ps and th = 25 ps. The clock rises at t = 3 ns.

1.
Window width: 90 + 25 = 115 ps.
2.
It opens at 3000 − 90 = 2910 ps and closes at 3000 + 25 = 3025 ps.
3.
D changing at 2900 ps or 3030 ps is safe. D changing at 2950 ps is inside the window and unsafe.
4.
In the diagram, the edge is at slot 5 and the 'stable' bar covers the two slots before it and two slots from it on.

Common mistakes

Taking the width as tsu alone, or as th − tsu. It's tsu + th.
Thinking D only has to be right at the exact moment of the edge.

Practice Setup-and-hold window

Interactive questions with instant feedback and a worked solution for every wrong answer.

Timing and Sequential Logic lesson full course

A flip-flop has tsu = 150 ps and th = 50 ps. How wide is the window around each clock edge during which D must not change, in ps?

Learn it step by step

Setup-and-hold window is taught in Timing and Sequential Logic and Latches and Flip-Flops.

Timing and Sequential Logic →Latches and Flip-Flops →

All terms