Metastability

Also called: metastable, metastable state

A flip-flop state stuck between 0 and 1 after D changes inside its setup-and-hold window. It resolves randomly and may take a long time.

A flip-flop stores a bit in a feedback loop that has two stable resting points, 0 and 1. If D changes inside the setup and hold window, the loop can get an almost perfectly balanced push and end up teetering between them. That's metastability.

Picture a ball on a hilltop between two valleys. It will roll into one valley eventually, because any tiny bit of noise tips it, but you can't say which valley or exactly when. Meanwhile the flip-flop's output may sit at an in-between voltage or take much longer than tcq to settle.

The key fact: the chance that it's still unsettled falls off exponentially with waiting time. Waiting a little longer makes failure dramatically less likely.

Inside a synchronous design, the setup and hold checks stop D from ever changing in the window, so metastability can't happen. The trouble is an asynchronous input, such as a push button or a signal from another clock domain. It has no fixed timing relationship to the clock, so sooner or later it will change inside the window. You can't prevent that; you can only contain it, with a two flip flop synchronizer.

Worked example

Example

Is this input change safe?

A flip-flop has tsu = 100 ps and th = 50 ps. Its clock rises at t = 1000 ps. D changes at one of three moments.

1.
The window runs from 1000 − 100 = 900 ps to 1000 + 50 = 1050 ps.
2.
D changes at 850 ps: before the window. Safe; the new value is captured.
3.
D changes at 960 ps: inside the window. The flip-flop may go metastable.
4.
D changes at 1080 ps: after the window. Safe; the old value is captured and the new one waits for the next edge.

Common mistakes

Thinking a metastable flip-flop always ends up at the 'right' value. It settles randomly to 0 or 1.
Believing a synchronizer removes metastability entirely. It makes failure extremely rare, not impossible.
Assuming careful timing analysis can protect an asynchronous input. Its timing is unknown, so it will eventually hit the window.

Practice Metastability

Interactive questions with instant feedback and a worked solution for every wrong answer.

Latches and Flip-Flops lesson full course

If D changes inside the setup-and-hold window, the flip-flop may become metastable: its output can hover between 0 and 1 for a while before settling.

Timing and Sequential Logic lesson full course

Practice exams

Learn it step by step

Metastability is taught in Timing and Sequential Logic and Latches and Flip-Flops.

Timing and Sequential Logic →Latches and Flip-Flops →

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