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Frequency divider

Also called: clock divider, frequency division, divide-by-two circuit, prescaler, clock prescaler

A circuit whose output repeats at a fraction of its input clock's frequency. A flip-flop that toggles every edge divides the frequency by 2.

A frequency divider takes a fast clock and produces a slower one. The simplest version is a single toggling flip-flop:

  • A T flip-flop with T = 1, a JK with J = K = 1, or a D flip-flop with wired to D.
  • Q flips at every rising clock edge, so one full cycle of Q (up and back down) takes two clock cycles.
  • Q's frequency is half the clock's, and its period is twice as long.

Chain them: use each stage's Q as the next stage's clock and each stage halves the frequency again. With n stages the last output runs at f / 2ⁿ. That chain is exactly an asynchronous (ripple) counter, read sideways.

Frequency and period are reciprocals (period = 1 / frequency), so halving one doubles the other.

Where you meet them: microcontroller timers use divider chains, called prescalers, to make slow ticks from a fast oscillator. A 32.768 kHz watch crystal divided by 2 fifteen times gives exactly one tick per second.

A divider by a number that is not a power of 2 needs a mod n counter instead of a plain chain.

CLKQ1Q2

Worked examples

Example

Reading the diagram above

Two T flip-flops with T = 1. The first is clocked by CLK; the second is clocked by Q1. Both start at 0.

  1. 1.

    CLK has a rising edge every 2 slots (slots 2, 4, 6, 8, 10). Q1 flips at each one.

  2. 2.

    Q1 repeats every 4 slots: half the clock frequency.

  3. 3.

    Q1 rises in slots 2, 6 and 10. Q2 flips at each of those.

  4. 4.

    Q2 repeats every 8 slots: a quarter of the clock frequency.

Example

How many stages?

T flip-flops with T = 1 are chained. How many stages turn a 48 MHz clock into 3 MHz?

  1. 1.

    Each stage divides by 2, so n stages divide by 2ⁿ.

  2. 2.

    48 MHz / 3 MHz = 16 = 2⁴.

  3. 3.

    4 stages. Check: 48 → 24 → 12 → 6 → 3 MHz.

Example

Period instead of frequency

A clock with a 4 ns period (250 MHz) drives a T flip-flop with T = 1. What are Q's frequency and period?

  1. 1.

    Q's frequency is half the clock's: 125 MHz.

  2. 2.

    Half the frequency means double the period.

  3. 3.

    Q's period is 8 ns. Check: 1 / 125 MHz = 8 ns.

Common mistakes

  • Halving the period instead of doubling it. A divide-by-2 makes the signal slower, so its period grows.

  • Adding the stages instead of multiplying. Three stages divide by 2 × 2 × 2 = 8, not 2 + 2 + 2 = 6.

  • Expecting a D flip-flop with D tied to 1 to divide the clock. It just loads 1 and stays there; D must be fed from Q'.

Practice Frequency divider

Interactive questions with instant feedback and a worked solution for every wrong answer.

Latches and Flip-Flops lesson full course

Counters lesson full course

And 6 more in the Counters lesson.

Practice exams

Related terms

Learn it step by step

Frequency divider is taught in Latches and Flip-Flops and Counters.

Latches and Flip-Flops →Counters →

All terms