Mod-N counter

Also called: mod-N, modulo-N counter, truncated counter, custom-modulus counter

A counter that steps through exactly N states, usually 0 to N − 1, and then returns to 0. N need not be a power of 2.

A mod-N counter has a modulus of N: it counts 0, 1, … , N − 1 and then goes back to 0. When N isn't a power of 2 it still needs the smallest n with 2ⁿ ≥ N flip-flops, and the codes from N to 2ⁿ − 1 become unused states.

There are three usual ways to build one:

Synchronous clear: watch for the last good state, N − 1. The clear waits for the next edge, which then goes to 0 instead of N.
Asynchronous clear: watch for the first bad state, N. The flip-flops clear at once, so N appears only as a brief glitch state. Cheap, but risky.
Design it directly: write a next-state table for the N real states and treat the unused codes as don't-cares when you simplify.

A loadable counter can also be shortened from the top: load S whenever the terminal count fires, which gives mod-(2ⁿ − S).

The single question that decides which state to detect: does the clear wait for the edge, or act straight away? Mod-N counters are everywhere as frequency dividers and timers.

Worked examples

Example

Mod-10 with a synchronous clear

Make a 4-bit synchronous up counter with a synchronous CLR count 0 to 9.

1.
Real states 0 to 9. The clear waits for an edge, so detect the last good state, 9 = 1001.
2.
Full decoding: CLR = .
3.
Among the visited states 0–9, only 8 and 9 have Q3 = 1, and only 9 also has Q0 = 1. So the partial decode CLR = works too.
4.
Trace: … 8 → 9 (CLR becomes 1) → next edge clears to 0. Ten states each last a full clock period ✓.

Example

Mod-12 with an asynchronous clear

A 4-bit ripple counter has active-low asynchronous clear pins, driven by a NAND gate.

1.
The clear acts at once, so detect the first bad state, 12 = 1100.
2.
Among 0 to 12, only 12 has Q3 = 1 and Q2 = 1, so the NAND needs just Q3 and Q2.
3.
When the count reaches 1100, the NAND output goes low and every flip-flop clears within nanoseconds.
4.
States lasting a full period: 0 to 11, twelve of them ✓. 1100 shows up only as a brief glitch.

Common mistakes

Detecting N with a synchronous clear. The counter sits in N for a whole period before clearing, giving mod-(N + 1).
Detecting N − 1 with an asynchronous clear. N − 1 is wiped out at once, giving mod-(N − 1).
Using a partial decode that also fires in another visited state. Check every state the counter really passes through.

Practice Mod-N counter

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Mod-N counter is taught in Counters.

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