Gate delay

Also called: gate delays, unit gate delay, gate delay model, unit delay

The time one logic gate takes to respond to an input change. Counting gate delays along a path gives a simple way to compare how fast circuits are.

No gate is instant. When an input changes, the output follows a short time later: that's its propagation delay. To compare designs without worrying about exact nanoseconds, we count in gate delays: the number of gates a signal passes through on its way from an input to an output.

The model used in this course's adder lessons:

every gate, XOR included, takes 1 gate delay
all inputs (every A and B bit, and C0) arrive at time 0
a gate's output is ready one delay after its latest input is ready

The slowest input-to-output path is the critical path, and its length is the circuit's worst-case delay.

The model is a simplification. Real gates differ (an XOR is slower than a NAND), and wide gates are slower than narrow ones. But it captures the key comparison: a ripple carry adder needs about 2 gate delays per bit, so its delay grows with the width, while a carry lookahead adder needs a fixed number of levels.

Read each question for what it counts. Some count only the carry path from C0 (2 per stage, 2n in total). Others count from the A and B inputs, which adds 1 for the first XOR (2n + 1).

Worked examples

Example

Timing one full adder

The full adder above, with A, B and C all arriving at time 0.

1.
Time 1: the first XOR () and the first AND () are ready. Both only need A and B.
2.
Time 2: the second XOR (S) and the second AND () are ready. Each waited for .
3.
Time 3: the OR gives Cout. It waited for the second AND.
4.
So S is ready at 2 and Cout at 3. From C alone, Cout takes only 2 (AND, then OR).

Example

Chaining the stages

In a ripple-carry adder, every stage's carry path is an AND then an OR, 2 gate delays. C1 is ready at 3, C2 at 5, C3 at 7: in general Cᵢ at 2i + 1.

Common mistakes

Adding up the delays of every gate instead of following the longest path.
Letting a gate start before its latest input is ready.
Mixing the carry-path count (2n) with the input-to-output count (2n + 1).

Practice Gate delay

Interactive questions with instant feedback and a worked solution for every wrong answer.

Adders and ALUs lesson full course

Practice exams

Learn it step by step

Gate delay is taught in Adders and ALUs and Timing and Sequential Logic.

Adders and ALUs →Timing and Sequential Logic →

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