A ripple-carry adder adds two n-bit numbers the way you do by hand: one column at a time, passing the carry left. It's n full adders in a row. Full adder i adds Aᵢ, Bᵢ and the carry Cᵢ, outputs the sum Sᵢ, and passes Cᵢ₊₁ to stage i + 1.
Carry numbering in this course: Cᵢ is the carry into bit i. So C0 is bit 0's carry-in (0 for plain addition, 1 when subtracting), C1 comes out of bit 0, and in a 4-bit adder C4 is the final carry out.
If C0 is always 0, bit 0 only adds two bits, so a half adder is enough there.
Strength: it's simple and small, just n identical cells.
Weakness: it's slow for wide numbers. Bit i can't settle until Cᵢ is right, which waits for Cᵢ₋₁, and so on down the chain. In the course's gate delay model, Cᵢ is guaranteed correct at 2i + 1 gate delays, so the delay grows linearly with n (see ripple carry delay). A carry lookahead adder removes that chain.
The same adder works for unsigned and twos complement numbers. With XOR gates on B it becomes an adder subtractor.